Semiconductor Memory Devices With ECC Engine
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Solution Overview
Problem
Current semiconductor memory devices face limitations in increasing error correction capability, particularly in densely packed 3D structures where traditional error correction methods are insufficient for effectively handling errors in both single and multi-bit data symbols.
Innovation Solution
The implementation of a semiconductor memory device with a memory cell array comprising normal and parity cell regions, coupled with an interface circuit that uses error correction code (ECC) engines to store and decode data, allowing for the correction of errors using shared parity check matrices, thereby enhancing error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional error correction methods are used in 3D stacked memory structures, then device integration is improved, but error correction capability deteriorates
Solution Approach 1:
The memory device is segmented into a normal cell array for storing main data and a separate parity cell array for storing parity data. This segmentation allows independent optimization of each array's function, enabling the parity array to be specifically dedicated to error correction operations while the normal array maintains high-density data storage, thus resolving the contradiction between integration density and error correction capability
Solution Approach 2:
A parity bit generation circuit is introduced as an intermediary component that generates parity bits based on main data and stores them in the parity cell array. This intermediary mechanism enables error correction by providing reference information (parity bits) that can be used to detect and correct errors in the main data without requiring complex error correction algorithms in the memory arrays themselves
2Productivity
If memory density is increased in 3D structures, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
Parity bits are generated and stored in the parity cell array before the actual data is written to or read from the normal cell array. This preliminary action of pre-computing and storing parity information enables error detection and correction to occur during data access operations, compensating for manufacturing defects that may occur during the high-density 3D stacking process
3Device complexity
If single ECC engine is used, then device complexity is reduced, but error correction versatility deteriorates
Solution Approach 1:
The parity cell array and associated parity generation circuit are designed to provide universal error correction capability that can handle multiple types of errors (single-bit errors, multi-bit errors, and symbol errors). This multi-functional design allows a single ECC system to address various error scenarios that would otherwise require multiple specialized ECC engines, maintaining low device complexity while achieving high error correction versatility
Data Source
AI summary
A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.