Semiconductor Memory ECC Circuit Scale Reduction
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Solution Overview
Problem
Conventional semiconductor devices with Error Checking and Correcting (ECC) functions experience a significant increase in circuit scale, particularly in wide bus configurations, due to the need for separate data latches and complex wiring for error detection and correction.
Innovation Solution
A semiconductor device design that includes a memory cell array, sense amplifiers, an error correction circuit with a syndrome generator, decoder, and error corrector, and a memory module interface circuit with a data retrieval clock generator and error detection signal determination clock, which allows for efficient error correction without increasing circuit scale by delaying data retrieval and sense amplifier activation only when errors are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate data latches and complex wiring are provided for error detection and correction, then error correction capability is improved, but circuit scale increases significantly
Solution Approach 1:
The patent merges the data latch and corrected data latch into a single shared latch structure. The latch can store either uncorrected data or corrected data based on control signals, eliminating the need for separate latch circuits for each data path. This merging approach maintains error correction capability while significantly reducing circuit scale, especially in wide bus configurations.
Solution Approach 2:
The single data latch is designed to serve multiple functions: it can latch uncorrected data during normal operation, latch corrected data when errors are detected, and switch between these states based on control signals from the error detection circuit. This multi-functionality eliminates the need for dedicated separate latches for different data states, reducing overall circuit complexity.
2Reliability
If 3-state buffer outputs and data memory outputs are exclusively controlled to create two paths on data bus, then error correction function is improved, but circuit scale increases due to dense and complicated wiring
Solution Approach 1:
The patent combines the data paths into a single unified data bus rather than maintaining separate exclusive paths. The same data bus is used for both uncorrected and corrected data transmission, with the error detection and correction circuitry operating on the data along the single bus path. This eliminates the need for separate wiring paths and reduces wiring complexity significantly.
Solution Approach 2:
The error detection and correction circuit acts as an intermediary processing stage on the data bus. Rather than creating parallel exclusive paths, the circuit intercepts data on the single data bus, performs error detection and correction operations, and returns the corrected data on the same bus. This intermediary approach maintains error correction functionality while using a single data bus, reducing wiring complexity.
Data Source
AI summary
There is provided a semiconductor device of which the circuit scale does not significantly increase even with an ECC function. A microcomputer having an internal flash memory inserts one weight in a sense amplifier activation signal only when an error detection signal is on the H level at a given time in a read cycle or when the error detection signal which was on the H level in a previous read cycle has shifted to the L level in a current read cycle. This allows the retrieval of output data signals after waiting till the output data signals through error correction are determined only when an error is contained in the output data signals.