Semiconductor Memory Device Embedded Region Parasitic Resistance
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Solution Overview
Problem
Increasing the number of stacked layers in semiconductor memory devices to enhance storage density leads to increased resistance in semiconductor columns, potentially causing issues with memory operations due to higher parasitic resistance along the memory string.
Innovation Solution
Incorporating an embedded region with a higher impurity concentration and thicker film thickness in the semiconductor layer, which reduces parasitic resistance and allows for a greater number of stacked layers without compromising memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers is increased to enhance storage density, then storage density is improved, but resistance of the semiconductor column is increased
Solution Approach 1:
The patent applies local quality by creating an embedded region with different impurity concentration and thickness characteristics within the semiconductor layer. This embedded region has a thicker film thickness and higher impurity concentration compared to the main body of the semiconductor layer, locally optimizing the electrical properties to reduce resistance in specific areas where it is most needed, thereby resolving the contradiction between increased storage density and increased resistance.
Solution Approach 2:
The patent changes physical parameters of the semiconductor layer by introducing an embedded region with modified impurity concentration and thickness. By adjusting these parameters locally within the semiconductor layer, the patent reduces the overall resistance of the semiconductor column while maintaining the increased number of stacked layers required for high storage density.
2Quantity of substance
If the number of stacked layers is increased to enhance storage density, then storage density is improved, but parasitic resistance is increased
Solution Approach 1:
The embedded region with higher impurity concentration and greater thickness is strategically positioned within the semiconductor layer to locally combat parasitic resistance. This localized modification targets the regions where parasitic resistance most adversely affects memory operations, allowing the patent to increase stacked layers for higher storage density while mitigating the harmful parasitic resistance effect.
Solution Approach 2:
The patent converts the harmful effect of increased parasitic resistance (which naturally occurs with more stacked layers) into a benefit by introducing the embedded region. The higher impurity concentration and increased thickness in the embedded region actively reduce the parasitic resistance, transforming what would be a harmful side effect into a beneficial characteristic that enables higher storage density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The embedded region effectively reduces ON resistance, enabling a higher storage density by allowing more stacked layers while maintaining efficient data writing and reading capabilities.
Implementation Method 1
The first region has a first thickness along the second direction from the outer periphery of the core member and a first impurity concentration, and a second region adjacent to the first region in the first direction has a second thickness along the second direction from the outer periphery of the core member that is greater than the first thickness and a second impurity concentration that is higher than the first impurity concentration
Data Source
AI summary
A semiconductor memory device includes conductive layers and insulation layers alternately stacked along a first direction. A core member extends through the insulation layers and conductive layers. A semiconductor layer on an outer periphery of the core member has a first region facing a conductive layer of the stack and a second region adjacent to the first region and facing an insulation layer. The first region has a first thickness and a first impurity concentration. The second region has a second thickness that is greater than the first thickness and a second impurity concentration that is different from the first impurity concentration. A charge accumulation film is between the semiconductor layer and the conductive layer in a second direction crossing the first direction.