3D Semiconductor Memory Epitaxial Layer Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of two-dimensional or planar semiconductor memory devices is limited by the cost and complexity of fine pattern forming technologies, necessitating the development of three-dimensional semiconductor memory devices with improved electric characteristics and miniaturization.
Innovation Solution
A semiconductor memory device with three-dimensionally arranged memory cells, featuring a substrate with an epitaxial layer and a gate stack, where the epitaxial layer's top surface is positioned higher than the substrate's surface, and a channel hole penetrating the gate stack, allowing for enhanced integration and electric connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor memory devices are used, then manufacturing process is simpler, but integration is limited by area occupied by unit memory cell
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical direction, with gate stacks positioned at different heights, enabling increased integration density without proportionally increasing the planar area occupied by each unit memory cell.
2Productivity
If fine pattern forming technology is advanced to increase integration, then integration improves, but process equipment cost increases
Solution Approach 1:
The memory device is segmented into multiple discrete gate stacks positioned at different vertical levels. Each gate stack functions as an independent memory cell unit, allowing the overall integration density to be increased by adding more stacked units rather than continuously refining the pattern size of individual cells.
3Productivity
If three-dimensional semiconductor memory devices are implemented, then integration increases, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension to stack multiple memory cells, achieving higher integration density. The gate stacks are arranged at different heights along the vertical axis, with channels extending through multiple gate stacks, enabling three-dimensional integration while maintaining manufacturability through systematic structural design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables increased integration and improved electric characteristics, addressing the limitations of two-dimensional devices while reducing the size and cost of semiconductor memory devices.
Implementation Method 1
the substrate comprises an epitaxial layer in the substrate below the channel hole
Data Source
AI summary
A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.