Semiconductor Memory Erase Control with Sequential Threshold Verification
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently and reliably performing erase operations, particularly in NAND flash memory, due to variations in threshold voltage distributions of memory cell transistors, which can lead to degradation and unusable blocks if not properly managed.
Innovation Solution
The semiconductor memory device employs a control circuit that executes a sequential process of first and second erase processes and verify processes to manage threshold voltage distributions, ensuring that a predetermined number of memory cells meet the verify voltage criteria, thereby preventing degradation and identifying potential bad blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single erase process and verify process is executed, then the erase operation is simple and fast, but the reliability of erase completion is insufficient due to threshold voltage variations
Solution Approach 1:
The patent divides the erase operation into multiple sequential erase processes (first erase process, second erase process) with intermediate verification steps. This segmentation allows the system to check threshold voltage distributions at different stages and determine whether additional erase operations are needed, thereby improving reliability without unnecessarily increasing complexity for all cases.
Solution Approach 2:
The patent implements a feedback mechanism where the verify process measures the threshold voltage distribution of memory cells after the first erase process, and based on this feedback, the control circuit determines whether to execute a second erase process. This feedback-driven approach ensures reliable erase completion while avoiding unnecessary additional erase operations.
2Reliability
If multiple erase processes are executed to ensure complete erasure, then erase reliability is improved, but the operation time increases
Solution Approach 1:
The patent applies partial action by executing a second erase process only when the verify process indicates that the first erase process was insufficient (i.e., when some memory cells still have threshold voltages above the verify voltage). This approach ensures complete erasure reliability while minimizing the time loss by avoiding unnecessary second erase operations for memory cells that were already properly erased.
3Manufacturing precision
If a verify process is performed after erase to check threshold voltage, then erase quality is ensured, but the operation complexity and time increase
Solution Approach 1:
The patent performs a verify process after the first erase process as a preliminary check before deciding whether to execute a second erase process. This preliminary verification ensures that the system only performs additional erase operations when necessary, thereby maintaining high erase quality precision while avoiding unnecessary operational complexity.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes memory cells and a control circuit configured to control an erase operation on the memory cells. The control circuit sequentially executes, in the erase operation, a first erase process, a first erase verify process, a second erase process, and a second erase verify process on the memory cells, acquires, in the first erase verify process, first memory cells having a threshold voltage equal to or lower than a first verify voltage, from among the memory cells, acquires, in the second erase verify process, the number of second memory cells having a threshold voltage higher than the first verify voltage, from among the first memory cells, and determines whether the number of the second memory cells is larger than a first value or not.