Semiconductor Memory Erase Operation via Channel Precharging
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high-speed and low-power erase operations, particularly in increasing the voltage of the vertical channel layer efficiently during the erase process, which affects the operating speed and efficiency of the device.
Innovation Solution
The proposed solution involves a precharge step where the vertical channel layer is precharged with electrons by applying a ground voltage to the bit line and a pass voltage to the word lines, followed by an erase voltage that generates a gate-induced drain current, allowing for a faster increase in voltage and improved erase operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional erase operation is performed without precharging the channel, then the power consumption is lower, but the erase operation speed is slower and the time to reach reference voltage is longer
Solution Approach 1:
The patent applies preliminary action by precharging the channel with electrons before performing the erase operation. A pass voltage is applied to the word line and a ground voltage to the bit line to inject electrons into the channel, creating a precharged state. This preliminary electron injection reduces the time required to reach the reference voltage during the subsequent erase operation, thereby improving erase speed without significantly increasing overall power consumption.
2Speed
If the voltage of the vertical channel layer is increased slowly during erase operation, then the power consumption is reduced, but the operating speed of the device decreases
Solution Approach 1:
The patent uses preliminary action by precharging the channel with electrons before the erase operation. This initial electron injection creates a head start for the voltage increase during erase, allowing the channel voltage to reach the reference voltage faster without requiring excessive power during the actual erase process.
Solution Approach 2:
The patent applies parameter changes by carefully controlling the voltage parameters during different phases. A pass voltage (higher than ground) is applied to the word line during precharging, and then an erase voltage (higher than pass voltage) is applied during the erase operation. This staged parameter change optimizes both speed and power consumption by matching the voltage level to the operational phase.
3Productivity
If the time to reach reference voltage is reduced, then the erase operation efficiency is improved, but the power consumption may increase
Solution Approach 1:
The patent achieves improved productivity by performing preliminary electron injection into the channel before the erase operation. This precharging step, though requiring some power, significantly reduces the time and power needed during the actual erase operation to reach the reference voltage, resulting in net improved erase operation efficiency with controlled power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required to reach the reference voltage during the erase operation, enhancing the operating speed and efficiency of the semiconductor memory device while maintaining low power consumption.
Implementation Method 1
generating a gate induced drain current (GIDL) current by applying an erase voltage to the bit line and the pass voltage to the word lines
Data Source
AI summary
Disclosed is an erase operation method of a semiconductor memory device which includes a cell string disposed between a bit line and a common source line and connected with a plurality of word lines. The operation method includes precharging a channel of the cell string by applying a ground voltage to the bit line and applying a pass voltage to the word lines, and generating a gate induced drain current (GIDL) current by applying an erase voltage to the bit line and the pass voltage to the word lines, and the pass voltage is greater than the ground voltage, and the erase voltage is greater than the pass voltage.