Semiconductor Memory Device Error Correction Circuit Area Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices with non-volatile memory cell arrays require a large area for error correction, which hinders productivity and chip size reduction.
Innovation Solution
A semiconductor memory device incorporating a dynamic random access memory (DRAM) cell array, a parity bit generator, a nonvolatile memory cell array, and an error correction circuit that generates and uses parity bits to correct data, allowing for the selection of spare cells and lines, thereby reducing the area occupied by the error correction circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a non-volatile memory cell array is used to activate redundancy cell arrays when defective cells are included, then reliability is improved, but the area of the memory device increases
Solution Approach 1:
The patent pre-calculates and stores syndrome values in a lookup table during the design phase. These syndrome values are used during operation to quickly identify and correct defective cells without requiring complex real-time computation, thereby reducing the area needed for error correction circuitry while maintaining reliability
Solution Approach 2:
The error correction functionality is segmented into discrete syndrome values stored in a lookup table rather than implementing a complete error correction algorithm. This segmentation allows the system to store only essential correction data, reducing the area occupied by the non-volatile memory cell array while preserving the ability to correct defects
2Reliability
If error correction circuits are included to correct errors in memory cells, then reliability is improved, but the area of the memory device increases
Solution Approach 1:
The syndrome values required for error correction are pre-calculated and stored in a lookup table during the design phase. During operation, the system simply retrieves the pre-computed syndrome value based on the received data, avoiding the need for complex real-time error correction computation circuits and reducing the overall area
Solution Approach 2:
Instead of implementing the complete error correction algorithm in hardware, the patent uses a lookup table that contains pre-computed syndrome values. This copying approach stores only the essential correction information in a compact format, significantly reducing the area required for error correction functionality while maintaining reliability
Data Source
AI summary
A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.