3D Semiconductor Memory Fabrication via Selective Epitaxy
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Solution Overview
Problem
The manufacturing of three-dimensional semiconductor memory devices faces challenges in achieving low-cost, mass-production while maintaining or exceeding the operational reliability of their two-dimensional counterparts, primarily due to the high costs associated with fine patterning technology used in two-dimensional devices.
Innovation Solution
A method involving the formation of a channel hole in a vertical stack of alternating insulating and sacrificial layers, followed by selective epitaxial growth to create a lower semiconductor pattern that protrudes vertically, with a channel structure penetrating the stack and an insulating gapfill pattern inside, allowing for the replacement of sacrificial layers with gate electrodes, thereby optimizing device integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor devices are manufactured using conventional fine patterning technology, then device integration is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar device architecture to three-dimensional vertical stacking, where memory cells are arranged in multiple layers along the vertical direction. This dimensional change allows higher device integration without requiring finer lateral patterning, thereby avoiding the cost increase associated with advanced fine patterning technology while achieving improved productivity through greater storage capacity per chip area.
2Ease of manufacture
If three-dimensional semiconductor devices are manufactured with simplified processes, then manufacturing cost is reduced, but operational reliability deteriorates
Solution Approach 1:
The patent divides the three-dimensional device fabrication into distinct sequential stages: forming sacrificial layers, creating channel holes, performing selective epitaxial growth to form semiconductor patterns, removing sacrificial layers, and forming gate electrodes. This segmentation allows each process step to be optimized independently using conventional manufacturing techniques, maintaining operational reliability while keeping individual process complexities manageable and manufacturing costs controlled.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that facilitate the formation of the three-dimensional architecture. These sacrificial layers are temporarily inserted during fabrication to define channel hole positions and protect underlying structures, then selectively removed to create voids for gate electrode formation. This intermediary approach enables complex 3D structuring using simpler conventional processes, maintaining reliability while reducing manufacturing complexity.
3Ease of manufacture
If conventional two-dimensional device architecture is used, then manufacturing cost is kept low, but device integration is limited
Solution Approach 1:
The patent employs vertical stacking to create multiple layers of memory cells along the thickness direction of the substrate, transforming the conventional two-dimensional planar arrangement into a three-dimensional structure. This allows multiple bit lines and word lines to be stacked vertically, enabling significantly higher device integration (more storage cells per chip area) while using the same conventional manufacturing processes, thus improving productivity without increasing manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of three-dimensional semiconductor memory devices with improved integration and operational reliability, reducing manufacturing costs and enhancing electron mobility, thus overcoming the limitations of two-dimensional devices.
Implementation Method 1
A selective epitaxial growth process can be performed to grow a lower semiconductor pattern from a top portion of the substrate that is exposed by the channel hole
Data Source
AI summary
A method of fabricating a semiconductor device can include forming a channel hole in a vertical stack of alternating insulating and sacrificial layers to form a recess in a substrate. A selectively epitaxial growth can be performed to provide a lower semiconductor pattern in the recess using material of the substrate as a seed and a recess can be formed to penetrate an upper surface of the lower semiconductor pattern via the channel hole.