Semiconductor Memory Failure Simulation for Controller Evaluation
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Solution Overview
Problem
The reliability of non-volatile memory devices, such as NAND flash memory, is compromised by miniaturization and increased integration, leading to complex operation verification and difficulty in identifying failures due to the increased variety and location of potential defects.
Innovation Solution
An evaluation method and device that simulates failure states in non-volatile memory devices, using a fault dictionary and physical location table to generate fault injection information, allowing controllers to operate under simulated failure conditions for efficient evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-volatile memory is miniaturized and highly integrated to increase capacity, then storage capacity increases, but operation verification becomes more complex and time-consuming
Solution Approach 1:
The patent creates a virtual copy of the non-volatile memory device through a simulation unit that replicates memory operations without requiring physical hardware. This virtual model allows comprehensive verification of controller operations under various failure conditions without the complexity and time costs of physical testing, directly resolving the contradiction between increased capacity and verification complexity
Solution Approach 2:
The patent introduces an evaluation device as an intermediary between the controller and the non-volatile memory. This intermediary contains a simulation unit that can emulate memory behavior including failure states, allowing verification without direct physical access to the memory device. This mediator simplifies the verification process by abstracting away the physical complexity while maintaining operational accuracy
2Quantity of substance
If non-volatile memory is highly integrated with increased capacity, then storage capacity increases, but the time required for operation verification increases
Solution Approach 1:
The patent pre-configures the simulation unit with various failure scenarios and memory operation models before actual verification begins. By preparing the virtual environment and failure conditions in advance, the system can immediately begin comprehensive verification without the time-consuming setup required for physical testing, thus reducing verification time while maintaining thoroughness
Solution Approach 2:
The virtual simulation unit creates a digital replica of memory operations that can be tested instantly without physical constraints. This copying approach allows parallel testing of multiple failure scenarios simultaneously, dramatically reducing the total verification time compared to sequential physical testing while fully supporting high-capacity memory verification
3Quantity of substance
If the variety and location of potential failures increase in highly integrated memory, then storage capacity increases, but difficulty in verifying controller operation under failure conditions increases
Solution Approach 1:
The simulation unit is designed with universal functionality to emulate any memory failure type and location through configurable parameters. Rather than requiring separate physical test setups for each failure mode, the single simulation unit can be programmed to represent any failure scenario, making verification of controller operations under diverse failure conditions straightforward and systematic
Solution Approach 2:
The patent uses parameter changes to represent different failure conditions in the simulation. By modifying virtual parameters such as memory cell states, bit error patterns, and location identifiers within the simulation unit, the system can easily transition between different failure scenarios without physical reconfiguration, significantly reducing the difficulty of verifying controller operations under various failure conditions
Data Source
AI summary
An evaluation method includes acquiring first information indicating a state of a defect of a defect of a semiconductor device; generating third information including a location of a failure and a type of the failure in the semiconductor device based on the first information and prestored second information, the prestored second information indicates that the location of the failure and the type of the failure are associated with the first information; controlling whether fourth information for specifying the type of the failure of the semiconductor device is returned to a control device for controlling the semiconductor device, based on an access request from the control device and the third information; and evaluating an operation of the control device after the fourth information is returned.