Semiconductor Memory Device with Flag Cell Access Control
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices have a large circuit size due to the negative voltage application circuit, which limits miniaturization and increases power consumption.
Innovation Solution
A semiconductor memory device with independently accessible non-volatile memory cores, each containing flag cells and data cells, where the access control circuit selects memory cores based on flag values, allowing for reduced circuit size by eliminating the need for data erasure circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a negative voltage application circuit is included to enable data erasure in conventional non-volatile memory, then data erasure capability is achieved, but circuit size increases and power consumption increases
Solution Approach 1:
The patent extracts and removes the negative voltage application circuit from the non-volatile memory device. By eliminating this circuit component entirely, the invention achieves circuit size reduction while maintaining data storage functionality through a simplified architecture that uses only positive voltage application for data writing.
Solution Approach 2:
The patent employs a one-way data writing mechanism where data can be written but not erased or rewritten. This disposable approach to data storage eliminates the need for complex erasure circuits, reducing circuit size while accepting that stored data remains permanent until power is removed.
2Ease of manufacture
If a negative voltage application circuit is included to enable data erasure in conventional non-volatile memory, then data erasure capability is achieved, but power consumption increases
Solution Approach 1:
The patent removes the negative voltage application circuit that consumes power during data erasure operations. By eliminating this power-consuming component and its associated operations, the invention significantly reduces overall power consumption while maintaining essential data storage functionality.
Solution Approach 2:
The one-way data writing mechanism accepts permanent data storage without erasure capability, eliminating the need for power-consuming erasure operations. This approach trades data permanence for reduced power consumption, suitable for applications where data is written once and read multiple times.
3Ease of manufacture
If the negative voltage application circuit occupies a large circuit area, then data erasure function is provided, but miniaturization is limited
Solution Approach 1:
The patent extracts the large-area negative voltage application circuit from the memory device architecture. This removal directly enables miniaturization by eliminating the primary space-consuming component, allowing the device to be scaled down for compact applications.
Solution Approach 2:
The patent segments the memory functionality into essential data storage and access operations, separating these from the non-essential data erasure function. This segmentation allows the core memory array to be minimized while eliminating auxiliary erasure circuitry that would otherwise increase device size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces circuit size and eliminates the need for data erasure circuits, enabling miniaturization and lower power consumption while allowing for data rewriting without the limitations of conventional non-volatile memory devices.
Implementation Method 1
A potential difference between the positive voltage and the negative voltage applied to the control gate and the source of each memory cell causes electrons, which are held in the floating gate of each memory cell, to move to the source region through Fowler-Nordheim tunneling.
Data Source
AI summary
A semiconductor memory device includes a plurality of independently accessible memory cores. Each memory core includes at least one flag cell storing a flag value and a plurality of data cells storing data. An access control circuit included in the semiconductor memory device selects an access-control subject memory core from the memory cores based on the flag value of the at least one flag cell of each memory core.