Semiconductor Memory Device With Floating Gate Electrodes

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Solution Overview

Problem

Current semiconductor memory devices face challenges in achieving high integration density of memory cells, particularly in stacked configurations, where the integration of memory cells in the plane structure is limited by the spacing and arrangement of interconnects and silicon pillars.

Innovation Solution

The semiconductor memory device employs a configuration with memory trenches and through-holes that allow for the formation of floating gate electrodes and tunnel insulating films, along with a specific arrangement of interconnects and insulating layers, enabling independent control of memory cells and increasing integration density by optimizing the array density of memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the spacing between interconnects and silicon pillars is reduced to increase integration density, then the number of memory cells per unit area increases, but the manufacturing precision and reliability of individual memory cells deteriorate

Engineering Contradiction:

Improveintegration density of memory cellsVSAvoidspacing control between interconnects and pillars

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional stacked configuration. Multiple memory cell stacks are vertically arranged, with interconnects and silicon pillars extending in the vertical direction. This dimensional change allows integration density to increase without proportionally reducing lateral spacing, as the density gain comes from the vertical stacking of multiple memory cell layers.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If the interval between memory trenches is reduced to increase the number of silicon pillars, then productivity and integration density improve, but the structural stability and electrical isolation between adjacent memory cells worsen

Engineering Contradiction:

Improvemanufacturing efficiency of memory cell formationVSAvoidelectrical isolation between memory cells

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements a nested structure where tunnel insulating films are formed within memory holes that are themselves within memory trenches. Multiple insulating layers (tunnel insulating film, charge storage layer, blocking insulating film) are nested within the trench structure. This nested arrangement provides robust electrical isolation even when trench intervals are reduced, as each memory cell is surrounded by multiple protective insulating barriers.

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent introduces floating gate electrodes as intermediary structures between adjacent memory cell stacks. These floating gates extend in the vertical direction and act as electrical barriers that prevent interference between neighboring memory cells. The floating gates serve as mediators that maintain electrical isolation without requiring large horizontal spacing between trenches.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If the array density of memory cells is increased through optimized interconnect and pillar arrangement, then integration density improves, but the device complexity and manufacturing process difficulty increase

Engineering Contradiction:

Improvearray density of memory cellsVSAvoidstructural complexity of interconnect and pillar configuration

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent designs interconnects and silicon pillars to serve multiple functions simultaneously. The vertical interconnects provide both electrical connection and structural support for stacked memory cell layers. The silicon pillars serve as both the memory cell substrate and the structural framework for forming memory holes. This multi-functionality reduces the number of separate components needed, simplifying the overall device structure despite high integration density.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent divides the memory device into multiple independent memory cell stacks arranged in an array. Each stack is a self-contained unit with its own memory holes, floating gates, and interconnects. This segmentation allows for modular manufacturing where identical structures can be replicated across the device, reducing process complexity through standardization even as the total number of memory cells increases.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9735167B2Semiconductor memory device and method for manufacturing the same

Publication Date: 2017.08.15 KIOXIA CORP

AI summary

A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a second direction crossing the first direction, a plurality of semiconductor pillars arrayed in a row along the first direction in each of spaces among the first interconnects and extending in a third direction crossing the first direction and the second direction, a first electrode disposed between one of the semiconductor pillars and one of the first interconnects, a first insulating film disposed between the first electrode and one of the first interconnects, a first insulating member disposed between the semiconductor pillars in the first direction and extending in the third direction and opposed the first interconnects not via the first insulating film.