Semiconductor Memory Structure With Gate-All-Around Word Line
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) experiences increased sub-threshold leakage, gate-induced drain leakage (GIDL), and leakage current between word lines due to shrinking integrated circuit sizes, leading to retention time losses.
Innovation Solution
A semiconductor memory structure is formed with a buried bit line, Gate-all-around structure, and self-aligned contact, which reduces leakage currents by isolating active regions and arranging the word line to not overlap with source/drain regions, and a honeycomb-shaped capacitor to increase memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integrated circuit size is reduced to increase memory density, then the memory density is improved, but the leakage current increases causing loss of retention time
Solution Approach 1:
The active region is divided into first and second active regions separated by a trench structure. This segmentation isolates the regions to prevent leakage current between them, addressing the retention time issue while maintaining high density through compact arrangement
Solution Approach 2:
The word line completely surrounds the first and second active regions in a nested configuration. This Gate-all-around structure provides superior gate control over the channel, effectively reducing sub-threshold leakage and GIDL while maintaining small footprint for high density
2Ease of manufacture
If the word line overlaps with source/drain regions to simplify manufacturing, then the ease of manufacture is improved, but the gate-induced drain leakage increases
Solution Approach 1:
Instead of having the word line overlap with source/drain regions, the word line is positioned to completely surround the active regions without overlapping the source/drain extensions. This inverted arrangement eliminates GIDL while the self-aligned deposition process maintains manufacturing simplicity
3Ease of manufacture
If conventional contact formation methods are used, then the ease of manufacture is maintained, but the process complexity increases and alignment precision decreases
Solution Approach 1:
The contact holes are formed using self-aligned deposition where the contact material is deposited conformally and then etched back. The process uses the existing trench structure and word line positioning to automatically define contact locations, eliminating the need for separate alignment steps and reducing process complexity
Data Source
AI summary
A method for forming a semiconductor memory structure includes forming an isolation structure surrounding an active region in a substrate. The method also includes forming a first trench to separate the active region into a first active region and a second active region. The method also includes forming a bit line over the bottom portion of the first trench. The method also includes forming a word line surrounding the first active region and the second active region and over the bit line. The method also includes self-aligned forming a contact over the first active region and the second active region. The method also includes forming a capacitor over the contact.