Semiconductor Memory Device Gate Contact Isolation
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Solution Overview
Problem
The manufacturing process of semiconductor memory devices is complicated due to differences in MOS transistor structures between memory cells and other transistors on the same chip, leading to integration challenges and reduced production yield.
Innovation Solution
A cleaning treatment is performed on the storage node contact in the memory cell region before forming the first metal silicide layer, ensuring the surface is free of impurities, and a gate contact opening is formed in the peripheral region to isolate the gate structure from this treatment, allowing for integrated process management and improved yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a cleaning treatment is performed on the storage node contact before forming the metal silicide layer, then the quality of the metal silicide layer is improved, but the gate structure in the peripheral region may be damaged by the cleaning treatment
Solution Approach 1:
The substrate is divided into a memory cell region and a peripheral region, with the cleaning treatment selectively applied only to the memory cell region where storage node contacts are located. The peripheral region containing gate structures is excluded from the cleaning treatment, thus protecting it from damage while still achieving clean surfaces for metal silicide formation in the memory cell region.
Solution Approach 2:
Different regions of the substrate receive different treatments: the memory cell region undergoes cleaning treatment to ensure high-quality metal silicide layer formation, while the peripheral region is protected from cleaning to preserve the gate structure integrity. This localized approach allows each region to have the quality characteristics needed for its specific function.
2Adaptability or versatility
If different MOS transistor structures are used in memory cells and other regions to meet product specifications and density requirements, then the device performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into region-specific steps: memory cell region processing includes cleaning treatment before metal silicide formation, while peripheral region processing excludes this cleaning step. This segmentation allows different transistor structures to be manufactured with optimized processes for each region without requiring completely separate manufacturing lines.
Solution Approach 2:
The cleaning treatment is applied selectively to the memory cell region where it is needed for high-quality metal silicide layer formation, while the peripheral region is protected from this treatment. This local quality approach allows the manufacturing process to be adapted to the specific requirements of each region, maintaining device performance while managing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures the formation of a high-quality metal silicide layer on the storage node contact and protects the gate structure in the peripheral region, thereby simplifying the manufacturing process and increasing production yield.
Implementation Method 1
a cleaning treatment is performed to the storage node contact before forming the first metal silicide layer on the storage node contact in the memory cell region to remove impurities on the surface of the storage node contact
Implementation Method 2
a first metal silicide layer is formed on the storage node contact after the cleaning treatment
Data Source
AI summary
A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.