Simultaneous Gate Oxide Formation for Semiconductor Memory Cells
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the need for multiple mask steps to form different power domain devices on the same substrate, which increases costs and fabrication time, while forming high and low power logic devices with the same gate oxide compromises performance for cost savings.
Innovation Solution
Forming gate oxides and polysilicon for memory cells and supra low power devices simultaneously, while independently forming gate oxides for low, medium, and high power devices, and performing source/drain implants at the same time to optimize performance and reduce space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different mask steps are used to form different power domain devices with different gate sizes, then device performance and power domain differentiation are improved, but manufacturing cost and fabrication time increase
Solution Approach 1:
The substrate is divided into multiple power domains (first power domain with first gate oxide thickness, second power domain with second gate oxide thickness) that can be independently configured. This segmentation allows different gate oxide thicknesses to be formed in different regions using selective masking, enabling power domain differentiation while maintaining manufacturing flexibility.
Solution Approach 2:
Different gate oxide thicknesses are implemented in different local regions of the substrate corresponding to different power domains. The first gate oxide layer has a first thickness in the first power domain region, while the second gate oxide layer has a second thickness in the second power domain region, allowing local optimization of device characteristics for different power requirements.
2Adaptability or versatility
If different mask steps are used to form different power domain devices, then device performance is improved, but fabrication time increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the first gate oxide layer across the entire substrate, then selectively removing it in the second power domain region, and forming the second gate oxide layer only in the second power domain. This segmented approach allows parallel processing and reduces total fabrication time compared to sequential mask steps for each device type.
Solution Approach 2:
The first gate oxide layer is formed preliminarily across the entire substrate before selective removal. This preliminary formation allows subsequent selective etching and second gate oxide formation to proceed more efficiently, reducing the number of separate mask steps required and thereby reducing fabrication time.
3Ease of manufacture
If high and low power logic devices are formed with the same gate oxide to save mask steps, then manufacturing cost is reduced, but device speed deteriorates
Solution Approach 1:
Different gate oxide thicknesses are implemented in different local regions: a thinner first gate oxide thickness in the first power domain for high-speed devices, and a thicker second gate oxide thickness in the second power domain for low-power devices. This local differentiation allows each device type to have optimized performance characteristics while using a unified fabrication approach that reduces mask steps.
Solution Approach 2:
The gate oxide thickness parameter is varied locally across different power domains. By changing the gate oxide thickness from the first thickness to the second thickness in different regions, the patent achieves both cost reduction (through reduced mask steps) and performance optimization (through parameter differentiation) simultaneously.
Data Source
AI summary
The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates.