Semiconductor Memory Structure for Lower Gate Resistance
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Solution Overview
Problem
Existing semiconductor memory devices face issues with degraded cell current and device failure due to increased gate resistance, leading to parasitic voltage drops and insufficient programming voltages, particularly in advanced technologies with highly scaled dimensions.
Innovation Solution
A semiconductor memory structure design that includes direct WLP and WLR gate connections over active regions, with independent word lines for each bit, and a plurality of bit lines and bit line contacts to reduce effective gate and bit line resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate resistance is increased, then device structure can be simplified, but cell current degrades and device failure occurs
Solution Approach 1:
The word line is divided into multiple segments (first word line and second word line) that are independently connected to different active regions. This segmentation allows each segment to have its own dedicated connection path, reducing the effective gate resistance for each segment while maintaining overall structural organization.
Solution Approach 2:
Different connection configurations are provided for different active regions. Each active region has dedicated bit line contacts and word line connections tailored to its specific requirements, optimizing the local electrical characteristics and reducing gate resistance effects in each region.
2Quantity of substance
If highly scaled dimensions are used, then device density increases, but gate resistance increases causing parasitic voltage drops
Solution Approach 1:
The word line is segmented into multiple independently controllable segments, each with its own connection to active regions. This segmentation reduces the effective resistance path for each segment, compensating for the increased resistance that would otherwise result from highly scaled dimensions.
Solution Approach 2:
Dedicated bit line contacts and conductive paths serve as intermediaries between the word lines and active regions. These intermediary structures provide low-resistance connection paths that mediate the electrical signal transmission, reducing parasitic voltage drops in the highly scaled device.
3Ease of manufacture
If conventional word line connections are used, then manufacturing process is simpler, but effective gate resistance is high degrading cell current
Solution Approach 1:
The word line structure is segmented into multiple independent segments with dedicated connections to different active regions. This segmentation reduces the effective gate resistance and improves cell current while maintaining compatibility with conventional fabrication processes through systematic integration of the segmented architecture.
Solution Approach 2:
The connection architecture is extended into additional dimensional layers with bit line contacts and multi-level interconnects. This dimensional expansion provides parallel conduction paths that reduce effective resistance and improve power delivery to active regions.
Data Source
AI summary
A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.