3D Semiconductor Memory with Height-Differentiated Contacts

The patent transitions from planar 2D memory cell arrangement to 3D vertical stacking, enabling memory cells to be arranged in multiple layers above the substrate. This dimensional change increases storage capacity by utilizing the vertical space rather than only horizontal plane, allowing multiple bit lines and word lines to intersect at different heights to form three-dimensional crosspoint memory structures.

The patent implements nested structures where conductive layers are embedded within insulating layers, and memory cells are nested within the three-dimensional space formed by intersecting word lines and bit lines. The vertical stacking creates nested arrangements where lower-layer structures support upper-layer structures, efficiently utilizing the available space and reducing void formation.

The patent segments the memory structure into multiple functional layers stacked vertically, with each layer containing memory cells, word lines, and bit lines. This segmentation allows independent formation and optimization of each layer, enabling efficient access paths to be established from the substrate surface to memory cells at different heights through vertically stacked contact holes and conductive plugs.

The patent introduces intermediary structures such as contact holes, conductive plugs, and intermediate conductive layers that facilitate electrical connection between the peripheral circuit region and the stacked memory cell regions. These intermediaries bridge the height difference by providing vertical conduction paths through the insulating layers, maintaining access efficiency despite the increased vertical distance to memory cells.