Semiconductor Memory Device with In-Memory Logic Operations
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high-speed and low-power consumption operations, particularly in deep learning applications that require processing large amounts of data, due to limitations in data transfer and processing efficiency between nonvolatile memory and operation circuits.
Innovation Solution
A semiconductor memory device configuration that includes a nonvolatile memory, a read circuit array, a multiply-accumulate operator array, and a controller circuit, with specific bus widths and data distribution mechanisms to facilitate efficient data transfer and processing, allowing for high-speed operations without the need for bit width adjustments and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred from nonvolatile memory to operation circuit through conventional bus interfaces, then data transfer is possible, but processing speed is limited and power consumption increases due to bit width adjustments and intermediate processing
Solution Approach 1:
The patent segments the data transfer path into direct connections from memory cell arrays to operation circuits, eliminating intermediate bus interfaces. Each memory cell array is directly connected to corresponding operation circuits, allowing parallel data transfer and processing without sequential bit width adjustments, thereby increasing processing speed and reducing power consumption.
Solution Approach 2:
The operation circuits are designed to perform multiple functions including data reception, multiplication, accumulation, and output generation within a single integrated structure. This multi-functionality eliminates the need for separate processing stages and bit width adjustments, improving processing speed while reducing overall power consumption of the data processing system.
2Productivity
If conventional memory-processor architecture is used, then data storage and processing are separated, but data transfer efficiency is reduced and power consumption increases
Solution Approach 1:
The patent merges the memory storage function and data processing function into a single integrated architecture where operation circuits are embedded within the memory device. Data can be stored in memory cell arrays and processed by operation circuits without being transferred to external processors, eliminating energy loss from data transfer and improving overall data processing efficiency.
Solution Approach 2:
The memory device performs data processing operations internally using its own integrated operation circuits, rather than relying on external processors. This self-service capability allows the memory device to autonomously perform multiplication and accumulation operations on stored data, improving productivity while reducing the energy loss associated with external data transfer and processing.
3Speed
If bit width adjustments are performed before data processing, then data compatibility is ensured, but processing time is increased and speed is reduced
Solution Approach 1:
The patent performs bit width matching as part of the initial data storage process rather than as a separate pre-processing step. Data is stored in memory cell arrays with inherent bit width organization that matches the operation circuit requirements, eliminating the need for time-consuming bit width adjustments before processing and improving operation speed.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a nonvolatile memory, a read circuit array, a multiply-accumulate operator array, a first bus, an operation controller circuit, and a second bus. The read circuit array reads the data from the nonvolatile memory. The multiply-accumulate operator array receives the data read from the read circuit array. The first bus is connected between the read circuit array and the multiply-accumulate operator array and having a first bit width. The operation controller circuit is electrically connected to the multiply-accumulate operator array. The second bus is connected to the operation controller circuit and having a second bit width smaller than the first bit width.