Semiconductor Memory Device With Inclined Stacked Layers
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Solution Overview
Problem
Current semiconductor memory devices face challenges in miniaturization and voltage breakdown strength due to variations in lithography and interconnect pitch control, especially when conductive layers are stacked on inclined surfaces.
Innovation Solution
The semiconductor memory device employs a configuration where conductive layers and insulating layers are alternately stacked with specific intervals and thicknesses, allowing for reduced surface area and increased voltage breakdown margin by maintaining uniform intervals and thicknesses, even on inclined surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conductive layers are stacked on inclined surfaces to reduce surface area, then device miniaturization is achieved, but manufacturing precision deteriorates due to variations in lithography and interconnect pitch control
Solution Approach 1:
The patent transitions from two-dimensional planar stacking to three-dimensional stacked configuration with inclined surfaces. The conductive layers are arranged in multiple tiers at different angles, utilizing the third dimension (vertical stacking) to reduce the footprint area while maintaining manufacturability through controlled angular orientations
Solution Approach 2:
Different regions of the stacked conductive layers have different interval distances. Specifically, intervals between adjacent conductive layers are varied depending on their position in the stack, with closer intervals in certain regions and wider intervals in others, optimizing both area utilization and manufacturing precision locally
2Quantity of substance
If intervals between conductive layers are reduced to increase density, then device miniaturization is achieved, but voltage breakdown strength deteriorates
Solution Approach 1:
The patent implements non-uniform interval distribution among stacked conductive layers. Certain adjacent layers are positioned with smaller intervals to maximize density, while other pairs maintain larger intervals to preserve voltage breakdown strength. This localized variation in spacing optimizes both density and reliability
Solution Approach 2:
The patent varies the interval parameter between conductive layers based on their position in the stack. By changing the spacing parameter locally rather than maintaining a uniform distance, the design achieves higher overall density while preventing voltage breakdown in critical regions
Data Source
AI summary
A semiconductor memory device includes a substrate having a memory region and a peripheral region that are adjacent to each other, and a plurality of insulating layers and a plurality of wiring layers that are alternately formed on the memory region and the peripheral region of the substrate. On the memory region, the insulating layers and the wiring layers are alternately formed along a thickness direction of the memory device. On the peripheral region, first portions of the insulating layers and first portions of the wiring layers are alternately formed along the thickness direction and second portions of the insulating layers and second portions of the wiring layers are alternately formed along a lateral direction. A width of the second portion of each of the wiring layers in the lateral direction is greater than a thickness of the first portion of the wiring layer.