Semiconductor Memory Interface With Independent Data I/O Periods
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Solution Overview
Problem
Existing semiconductor systems face performance degradation due to increased command overhead in NAND interfaces and difficulty in parallel operations of NAND flash memory devices, particularly in high-frequency operations.
Innovation Solution
A semiconductor system with a first and second semiconductor apparatus, where the first apparatus provides chip enable and command address signals to the second apparatus, allowing independent data input/output periods for multiple memory dies through separate command address signal sets, enabling parallel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If NAND interface method transmits command address signal and data through the same input/output bus, then device complexity is reduced, but command overhead increases causing performance degradation
Solution Approach 1:
The patent segments the interface into two separate buses: a command address bus for transmitting command address signals and a data bus for transmitting data. This segmentation resolves the contradiction by reducing command overhead on the data bus while maintaining relatively simple interface structure through dedicated pathways for each signal type.
Solution Approach 2:
The patent introduces a command address signal set that acts as an intermediary to define the data input/output period. This intermediary mechanism coordinates between the command address bus and data bus, allowing efficient timing control without requiring constant overhead signals on the data path.
2Productivity
If separate command address (SCA) interface method transmits command address signal and data through different input/output buses, then command overhead decreases, but parallel operations of multiple NAND flash memory devices become difficult
Solution Approach 1:
The patent makes the command address bus universal by allowing it to serve multiple memory devices simultaneously. The command address signal set can selectively enable different memory devices (first, second, third memory devices) through the same bus, enabling parallel operations while maintaining the low overhead benefits of separate buses.
Solution Approach 2:
The patent implements dynamic selection of memory devices through the command address signal set. The ability to dynamically enable different memory devices (first, second, or third memory devices) based on the command address signals allows flexible parallel operations while using a fixed separate-bus architecture.
3Speed
If operating frequency of NAND flash memory system increases, then data transmission speed improves, but command overhead increases causing performance degradation
Solution Approach 1:
The patent uses periodic action through the second command address signal set that defines the data input/output period. This periodic timing mechanism allows high-speed data transmission during designated periods while systematically managing command overhead through structured timing intervals, preventing performance degradation even at high operating frequencies.
Data Source
AI summary
A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus provides the second semiconductor apparatus with a chip enable signal and a command address signal set, and the second semiconductor apparatus performs an internal operation based on the chip enable signal and the command address signal set. The first semiconductor apparatus provides the second semiconductor apparatus with a selection chip enable command, and the second semiconductor apparatus transmits data to the first semiconductor apparatus or receives the data from the first memory device after receiving the selection chip enable command.