3D Stacked Semiconductor Memory Device Insulating Layer Formation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently forming interconnect portions and insulating layers during manufacturing, leading to potential degradations in device characteristics due to miniaturization, such as increased processing difficulty and leakage current.
Innovation Solution
The semiconductor memory device employs a stacked structure with separate first and second electrode layers and insulating layers, where the second layers are removed through slits to form insulating portions between the stacked bodies, preventing interconnect formation in insulating layers and facilitating the creation of air gaps, thereby reducing processing complexity and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional manufacturing methods are used for forming interconnect portions and insulating layers, then device miniaturization is pursued, but processing difficulty increases and leakage current increases
Solution Approach 1:
The device is divided into first and second stacked bodies that are separately formed and then combined. The insulating layers are formed in separate stacked bodies before being integrated, which simplifies the manufacturing process by avoiding the need to form interconnect portions through the entire stacked structure at once. This segmentation approach reduces processing difficulty while enabling device miniaturization.
Solution Approach 2:
The patent transitions from planar device architecture to three-dimensional stacked architecture. By stacking multiple electrode layers and insulating layers vertically, the device achieves miniaturization in the planar dimensions while utilizing the vertical dimension for increased integration. The separate formation of stacked bodies in three-dimensional space simplifies the overall manufacturing process.
2Length of moving object
If conventional manufacturing methods are used for forming interconnect portions and insulating layers, then device miniaturization is pursued, but leakage current increases
Solution Approach 1:
By dividing the device into separate stacked bodies with insulating layers formed in each, the patent creates natural insulation barriers that prevent leakage current paths. The interconnect portions are confined to specific regions rather than extending through the entire device, which reduces parasitic leakage. This segmentation approach maintains electrical isolation while enabling miniaturization.
Solution Approach 2:
The insulating layers serve as intermediary elements between conductive electrode layers and interconnect portions. These insulating layers provide electrical isolation that prevents leakage current while allowing the device to be miniaturized. The intermediary insulating structure ensures proper electrical separation in the compact three-dimensional architecture.
3Reliability
If complex manufacturing processes are used, then device characteristics are maintained, but processing complexity increases
Solution Approach 1:
The manufacturing process is segmented into separate stages: forming the first stacked body with its insulating layers, forming the second stacked body with its insulating layers, and then combining them. This segmentation allows each stacked body to be optimized independently, maintaining device characteristics while reducing overall processing complexity compared to forming the entire structure in one complex process.
Solution Approach 2:
The insulating layers are formed in advance within each stacked body before the final assembly. This preliminary action ensures that the insulating structure is properly established early in the manufacturing process, which simplifies subsequent steps and reduces the need for complex post-processing to ensure proper insulation and electrical characteristics.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first stacked body including a plurality of first electrode layers and a plurality of first insulating layers, the first electrode layers separately stacked each other, the first insulating layers provided between the first electrode layers; a second stacked body including a plurality of second electrode layers and a plurality of second insulating layers, the second electrode layers separately stacked each other, the second insulating layers provided between the second electrode layers, the second stacked body separated from the first stacked body in a first direction crossing a stacking direction of the first stacked body; and a first insulating portion provided between the first stacked body and the second stacked body, the first insulating portion provided integrally to the first insulating layers and the second insulating layers.