3D Semiconductor Memory Device Integration Density
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Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in integration density due to the high cost and inefficiency of forming fine patterns, which restricts their performance and manufacturing costs.
Innovation Solution
A semiconductor memory device with a cell array region and a peripheral circuit region, featuring a body conductive layer, vertically stacked electrodes, and a remaining substrate with a buried insulating layer and a peripheral active layer, allowing for reduced thickness and increased integration density through advanced manufacturing processes such as etching and layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional two-dimensional semiconductor memory devices are used, then manufacturing processes are simpler, but integration density is limited
Solution Approach 1:
The patent transitions from conventional two-dimensional memory cell structures to a three-dimensional architecture where bit lines extend vertically through multiple layers. This dimensional change allows significantly higher integration density by utilizing the vertical space above the substrate, enabling more memory cells to be packed into the same footprint area while maintaining manufacturability through layer-by-layer fabrication processes
2Manufacturing precision
If fine patterns are formed to increase integration density, then manufacturing costs increase, but integration density improves
Solution Approach 1:
The patent segments the memory device into distinct functional layers including substrate layer, first bit line layer, insulating layer, second bit line layer, and cap layer. Each layer can be formed using separate, well-established manufacturing processes, avoiding the need for extremely high-priced apparatuses while achieving high integration density through the segmented three-dimensional structure
3Manufacturing precision
If device thickness is reduced, then integration density increases, but electrical characteristics may deteriorate
Solution Approach 1:
The patent achieves reduced device footprint (not thickness) by extending bit lines vertically in the third dimension. The multi-layer structure with insulating layers between conductive layers maintains proper electrical isolation and characteristics while increasing integration density, as the vertical bit line extension allows more cells per unit area without compromising electrical performance
Data Source
AI summary
A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.