3D Semiconductor Memory Integration Density and Reliability
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in integration density and reliability due to the high cost of equipment required for forming fine patterns, and 3D devices are expensive with concerns regarding reliable device characteristics.
Innovation Solution
A semiconductor memory device design featuring a substrate with alternately stacked insulating and gate patterns, a channel structure, charge storage structure, and contact structure, including specific barrier and blocking patterns, and metal patterns to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D semiconductor memory devices use fine pattern formation techniques to increase integration density, then integration density is improved, but manufacturing cost increases due to extremely high-priced equipment
Solution Approach 1:
The patent transitions from conventional 2D planar memory cells to 3D vertically stacked memory cells. Multiple memory cells are stacked in the vertical direction (third dimension) using alternating insulating patterns and gate patterns, enabling higher integration density without requiring finer lateral patterning that would demand expensive equipment.
Solution Approach 2:
The memory device is segmented into multiple stacked layers with insulating patterns and gate patterns alternately arranged vertically. Each stack forms an independent memory cell unit, allowing modular fabrication and reducing the complexity of forming fine patterns across the entire device area.
2Quantity of substance
If 3D semiconductor memory devices are produced to overcome integration density limitations, then integration density is improved, but manufacturing cost increases and device reliability becomes concerning
Solution Approach 1:
Barrier patterns are selectively formed at specific locations where gate patterns contact insulating patterns to prevent unwanted electrical conduction. Blocking patterns are placed between charge storage structures and gate patterns to control charge flow. These localized structural modifications improve device reliability without compromising the 3D stacked architecture's integration density.
3Reliability
If barrier patterns and blocking patterns are added to the gate structure, then device reliability is improved, but structural complexity increases
Solution Approach 1:
The barrier pattern is integrated into the gate pattern structure itself, forming a unified gate assembly. The blocking pattern is positioned between the charge storage structure and gate pattern in a way that combines multiple functions (charge blocking and structural support) into a single element, reducing overall structural complexity while maintaining reliability improvements.
Data Source
AI summary
A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.