Semiconductor Memory Cell With Inter-Gate Insulating Film
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Solution Overview
Problem
Three-dimensional memory cells with a floating gate and charge trapping film suffer from low erase speed and increased interference due to miniaturization, along with a low charge retaining ability due to charge leakage from the high-k charge trapping film to the floating gate.
Innovation Solution
Incorporating a floating gate and an inter-gate insulating film between the tunnel insulating film and the charge trapping film, with the charge trapping film configured as a high-k film to enhance charge storage, and using a semiconductor layer and insulating film combination for the charge storage layer to prevent charge leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a high-k film is used as the charge trapping film to store a large amount of charge, then the charge storing ability is improved, but charges are likely to leak to the floating gate resulting in low charge retaining ability
Solution Approach 1:
An inter-gate insulating film is introduced as an intermediary layer between the floating gate and the charge trapping film. This mediator prevents direct charge leakage from the high-k charge trapping film to the floating gate, thereby maintaining both high charge storing ability and good charge retaining ability.
Solution Approach 2:
The memory cell uses a composite structure combining a floating gate, an inter-gate insulating film, and a high-k charge trapping film. This composite material approach allows the system to achieve both high charge capacity and reliable charge retention by leveraging the complementary properties of different materials.
2Volume of moving object
If the memory cell is miniaturized to reduce size, then the device size is reduced, but interference between memory cells increases
Solution Approach 1:
The patent employs a three-dimensional stacked memory structure where memory cells are arranged vertically in multiple layers. This dimensional transition from planar to vertical architecture allows for higher storage density while maintaining sufficient spacing between cells to reduce interference effects.
3Speed
If a floating gate is added to the MONOS type memory cell to improve erase speed, then the erase speed is improved, but the structure becomes more complex and charge leakage occurs
Solution Approach 1:
The inter-gate insulating film serves as a mediator that enables the floating gate to function effectively for fast erase operations while preventing the harmful side effect of charge leakage. This allows the system to benefit from the floating gate's speed advantage without suffering from its complexity and reliability drawbacks.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween.