Semiconductor Memory Interconnect via XY Staggered Pattern
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Solution Overview
Problem
The manufacturing of semiconductor memory devices is time-consuming and costly due to the need for multiple masks to define vias in the peripheral regions, which complicates the formation of high-density interconnect structures required for shrinking device sizes.
Innovation Solution
A 3D semiconductor memory structure with a XY staggered pattern of vias and metal layers, allowing for the use of a single mask to form interconnect structures, thereby simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used to define vias in peripheral regions, then high-density interconnect structures can be formed, but manufacturing time and cost increase
Solution Approach 1:
The patent combines the definition of vias in peripheral regions with a single mask pattern, merging multiple via definition steps into one. The interconnect structure includes vias in both cell array regions and peripheral regions that are all defined by the same mask, eliminating the need for separate mask steps for peripheral vias and reducing total manufacturing time
Solution Approach 2:
The single mask serves multiple functions by simultaneously defining vias for both cell array regions and peripheral regions. This universal mask approach allows one mask layer to perform the work of multiple separate masks, reducing the number of photolithography steps required while maintaining via definition precision
2Manufacturing precision
If multiple masks are used to define vias in peripheral regions, then high-density interconnect structures can be formed, but manufacturing cost increases
Solution Approach 1:
The patent merges the via definition process for peripheral regions with the cell array via definition into a single mask step. This consolidation reduces the number of mask layers required, directly lowering material costs and process complexity while maintaining the ability to form high-density interconnect structures
Solution Approach 2:
The patent uses a single disposable mask layer that serves its purpose of defining all vias (both cell array and peripheral) in one go, rather than using multiple reusable mask layers. This approach reduces overall mask-related costs by eliminating the need for multiple expensive photolithography mask steps
3Volume of moving object
If device sizes are shrunk, then higher integration is achieved, but interconnect structure formation becomes more complex
Solution Approach 1:
The patent addresses device scaling by extending interconnect structures into the third dimension with stacked metal layers and vias. The interconnect structure includes multiple metal layers (first metal layer, second metal layer) stacked vertically, allowing high-density interconnection in a compact footprint while maintaining manufacturability through the single-mask via definition approach
Data Source
AI summary
A semiconductor memory structure and method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure comprises a cell array region, at least one connection region formed beside the cell array region and an interconnect structure formed on the connection region. The connection region comprises staircase portions and interval portions, which are alternately arranged and are separated by ferroelectric layers. The staircase portion comprises a staircase structure of alternating insulating layers and conductive layers, a dielectric layer formed on the staircase structure, and first conductive pillars formed over the staircase structure, extending into the dielectric layer and in contact with the staircase structure. The interval portion is formed beside the staircase portion and comprises second conductive pillars. The interconnect structure comprises vias formed on the first conductive pillars and the second conductive pillars in a XY staggered pattern.