3D Semiconductor Memory Interconnection Structures
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Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in integration due to the high cost and complexity of fine pattern forming technology, which restricts their ability to achieve higher integration and cost-effective manufacturing.
Innovation Solution
The semiconductor memory device incorporates interconnection structures that allow for easy connection of vertical electrodes, including horizontal and vertical electrodes stacked on a substrate, with specific contact and interconnection configurations that enable efficient electrical connectivity and higher integration without the need for expensive fine pattern forming equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pattern forming technology is used to increase integration of two-dimensional semiconductor memory devices, then integration is improved, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertical structures by stacking multiple electrode structures vertically. This dimensional change allows integration to be determined by the number of stacked layers rather than lateral pattern fineness, thereby improving integration without requiring expensive fine pattern forming equipment.
Solution Approach 2:
The memory device is divided into multiple discrete electrode structures that are stacked vertically. Each electrode structure contains horizontal electrodes and vertical electrodes that can be independently formed and connected, allowing the complex three-dimensional interconnection to be built up layer by layer through simplified sequential processing steps.
2Quantity of substance
If fine pattern forming technology is used to increase integration of two-dimensional semiconductor memory devices, then integration is improved, but manufacturing cost increases
Solution Approach 1:
By moving to three-dimensional stacking architecture, the patent enables integration scaling without relying on costly fine pattern forming processes. The vertical stacking approach uses standard lithography to form patterns that are then built up in the third dimension, significantly reducing equipment costs while achieving higher integration.
3Quantity of substance
If vertical electrodes are connected to horizontal electrodes in stacked electrode structures, then three-dimensional integration is achieved, but interconnection complexity increases
Solution Approach 1:
The interconnection structure is segmented into distinct functional components: first contacts connecting to horizontal electrodes, second contacts connecting to vertical electrodes, and interconnection lines linking them. This segmentation allows each component to be formed and optimized independently, simplifying the overall manufacturing process despite the three-dimensional complexity.
Solution Approach 2:
The patent introduces intermediate interconnection structures (first and second interconnection lines) that act as mediators between the horizontal and vertical electrode systems. These intermediate connections provide a systematic approach to routing signals in three dimensions, reducing the overall interconnection complexity by breaking down direct complex connections into simpler sequential steps.
Data Source
AI summary
A semiconductor memory includes electrode structures that each includes horizontal electrodes stacked on each other a substrate, vertical electrodes between the electrode structures and extending along the horizontal electrodes, first contacts connected to the horizontal electrodes at end portions of the electrode structures, second contacts connected to upper portions of the vertical electrodes, and a first interconnection structure connected to top surfaces of the second contacts. The first interconnection structure includes first and second sub-interconnection lines. The sub-interconnection lines extend in a first direction and contact the top surfaces of the second contacts. The second sub-interconnection lines extended in a second direction crossing the first direction and contact the first sub-interconnection lines.