Semiconductor Memory I/O Architecture for HCB Full-Duplex Access
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Solution Overview
Problem
Existing semiconductor memory devices face limitations in utilizing the advantages of hybrid copper bonding (HCB) and advanced packaging methods, particularly in the input/output structure, leading to challenges in high-speed connection and signal transmission.
Innovation Solution
Implementing a semiconductor memory device with a modified command combination and data path structure that supports full duplex access, utilizing hybrid copper bonding to eliminate serialization and deserialization processes, enabling simultaneous read and write operations through independent data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional micro bump connection method is used, then packaging structure is simple, but signal transmission speed is limited and connection path cannot be sufficiently shortened
Solution Approach 1:
The packaging structure is segmented into multiple layers with memory chips mounted on different levels. The first memory chip is mounted on the first surface of the substrate, and the second memory chip is mounted on the second surface, creating a multi-layer configuration that shortens signal transmission paths while maintaining structural organization
Solution Approach 2:
The patent transitions from a single-layer planar arrangement to a three-dimensional multi-layer structure by mounting memory chips on both surfaces of the substrate. This dimensional change allows simultaneous access to multiple chips, reducing latency and increasing bandwidth without requiring excessively long connection paths
2Productivity
If hybrid copper bonding HCB is applied, then high-speed connection is achieved, but input/output structure cannot fully utilize its advantages
Solution Approach 1:
The patent combines multiple functions into the I/O structure: the same pad structure handles both data transmission and command/address signals, and the multi-chip configuration enables simultaneous read and write operations. This merging allows HCB technology to achieve high bandwidth while managing complexity through functional integration
Solution Approach 2:
The I/O pads are designed with multi-functionality to handle various signal types (data, commands, addresses) and support full-duplex operations. The first and second memory chips can simultaneously perform read and write operations through the shared I/O structure, maximizing the utility of each component
3Loss of time
If serialization processing is used for data transmission, then data path is simplified, but latency increases and bandwidth is reduced
Solution Approach 1:
The patent extracts and eliminates the serialization processing stage from the data transmission path. Write data is transmitted in parallel from the external device directly to the first memory chip, and read data is transmitted in parallel from the second memory chip to the external device, removing the latency introduced by serialization and deserialization operations
Data Source
AI summary
A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory device, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input/output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing. In some embodiments, the semiconductor memory device is electrically and physically coupled to a central processing unit by hybrid copper bonding.