Semiconductor Memory Device Ion Implantation Masking
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Solution Overview
Problem
Existing flash memory device manufacturing processes face challenges with complex source structures leading to defects and insufficient thermal budget, resulting in poor uniformity and potential erase failures due to ion implantation defects and non-uniform ion diffusion.
Innovation Solution
A manufacturing method that performs lightly doped drain ion implantation on the memory area with a simpler physical structure, using a first layer as a mask to reduce ion blockage and incorporating thermal treatments to repair lattice damage, while eliminating the need for a photoresist in the peripheral area to save costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned source etching is performed to form the source structure, then the source structure is formed with alignment, but the structure becomes complex and defects such as particles are easily included
Solution Approach 1:
The invention extracts and removes the complex self-aligned source etching process from the manufacturing flow. By performing lightly doped drain ion implantation before source formation, the patent eliminates the need for subsequent source etching steps, thereby removing the source of defects while maintaining alignment through the mask layer.
Solution Approach 2:
The patent performs lightly doped drain ion implantation as a preliminary action before forming the source structure. This preliminary doping step is conducted when the mask layer is still present, allowing ion implantation through the mask without requiring complex subsequent etching operations to achieve alignment.
2Reliability
If multiple process steps including gate re-oxidation and self-aligned source etching are performed after ion implantation, then the source structure is formed, but the thermal budget is insufficient leading to unrepaired lattice damage
Solution Approach 1:
The invention performs lightly doped drain ion implantation before source formation and gate re-oxidation, allowing the subsequent gate re-oxidation process to serve dual purposes: forming the gate oxide and providing thermal treatment to repair ion implantation damage. This preliminary timing of ion implantation enables utilization of existing process thermal budgets.
Solution Approach 2:
The patent merges the function of gate re-oxidation with lattice damage repair. By timing the ion implantation beforehand, the gate re-oxidation process simultaneously achieves oxide formation and thermal annealing to repair implantation-induced lattice damage, eliminating the need for separate annealing steps.
3Manufacturing precision
If photo resist is used to cover the peripheral logic control area for selective ion implantation, then ion implantation is performed only on the memory area, but an additional photomask is required increasing manufacturing cost
Solution Approach 1:
The patent makes the mask layer serve multiple functions: it acts as both the gate structure for peripheral devices and as the mask for selective ion implantation into memory cells. This multi-functionality eliminates the need for separate photo resist masks, reducing manufacturing steps and costs while maintaining precise selective doping.
Solution Approach 2:
The invention merges the mask layer with the peripheral gate structure. The same mask layer that defines the peripheral transistor gates is utilized as the masking layer for ion implantation into memory cells, combining two previously separate functions into one unified structure and process step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the electrical uniformity of memory cells, enhances erase performance, and increases yield by reducing ion implantation defects and achieving more uniform ion diffusion without additional thermal budget, while reducing manufacturing costs.
Implementation Method 1
performing ion implantation to form a lightly doped drain on two sides of the memory gate structure
Implementation Method 2
incorporating thermal treatments to repair lattice damage, while eliminating the need for a photoresist in the peripheral area
Data Source
AI summary
The present invention provides a manufacturing method for a semiconductor memory device. The method comprises: providing a substrate, wherein a gate structure of a memory transistor is formed on a memory area of the substrate, and a first layer used for forming a gate structure of a peripheral transistor is formed on a peripheral area of the substrate; performing lightly doped drain ion implantation on an upper part of a portion, on two sides of the gate structure of the memory transistor, of the memory area of the substrate by applying the first layer as a mask of the peripheral area; and etching the first layer to form the gate structure of the peripheral transistor. According to the present invention, an ion diffusion degree of source and drain electrodes of the memory area may be effectively increased, and the uniformity of a memory cell device is improved.