3D Semiconductor Memory Stacking with Layer Transfer Alignment
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing and the limitations of Through-Silicon-Via (TSV) technology in achieving high vertical connectivity for 3D Integrated Circuits (ICs) pose challenges for device scaling and performance enhancement.
Innovation Solution
The use of layer transfer technologies, such as SmartCut and wafer bonding, to construct 3D ICs with monocrystalline channels and junction-less transistors, enabling precise alignment and reduced misalignment between memory cells, and the integration of resistance-based memory elements with select transistors, allowing for dense vertical interconnects and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon-Via (TSV) technology is used for 3D IC construction, then vertical connectivity is achieved, but the connectivity density is limited and development cost increases
Solution Approach 1:
The patent transitions from planar 2D IC architecture to three-dimensional stacked architecture, enabling vertical interconnects through TSVs that penetrate the substrate. This dimensional change allows multiple logic layers to be stacked above the memory layer, dramatically increasing connectivity density and enabling high-bandwidth memory interfaces without proportionally increasing TSV count.
Solution Approach 2:
The patent implements a nested structure where logic layers are stacked above the memory layer, with TSVs providing vertical interconnects through the substrate. The memory layer is embedded within the three-dimensional structure, surrounded by logic layers that access it through vertical interconnects, creating a nested arrangement that maximizes space utilization and connectivity.
2Ease of manufacture
If mask set cost is reduced for semiconductor manufacturing, then development cost decreases, but manufacturing precision may be compromised
Solution Approach 1:
The patent employs a single lithography mask set that serves multiple functions: defining memory cell structures in the memory layer, defining logic circuit structures in logic layers, and defining alignment marks across all layers. This universal mask set approach eliminates the need for separate expensive custom mask sets for each layer type, significantly reducing development costs while maintaining precise alignment through consistent reference marks.
Solution Approach 2:
The patent uses standard cell-based logic layer designs that can be replicated and copied across multiple logic layers without requiring custom mask sets. The same mask patterns used for memory layer definition are reused for logic layer definition, allowing standard library cells to be instantiated and stacked vertically, thereby reducing mask set costs while maintaining manufacturing precision through proven design reuse.
Data Source
AI summary
A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.