Semiconductor Memory Testing With Word-Line And Bit-Line Grouping
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently screening non-single bit defects, which can lead to decreased yield in DRAM chip production, as conventional methods fail to differentiate between single and non-single bit defects.
Innovation Solution
A semiconductor memory device with a parallel bit test circuit and a latch circuit that selectively latches outputs based on pass/fail determinations, allowing for the identification of non-single bit defects by evaluating groups of memory cells connected to the same word or bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a parallel bit test is performed to determine whether each memory cell is defective, then test coverage is improved, but single bit defects cause false positives that decrease production yield
Solution Approach 1:
The patent merges multiple memory cell test results that share common word lines or bit lines into a single aggregated test result. By combining individual cell outcomes (pass/fail) at the word line or bit line level, the system distinguishes between single cell defects and systematic defects affecting multiple cells, thereby reducing false positives while maintaining comprehensive test coverage.
2Device complexity
If conventional single bit defect determination is used, then test simplicity is maintained, but non-single bit defects cannot be identified leading to reduced yield
Solution Approach 1:
The patent segments the memory cell array into groups based on shared word lines or bit lines. By dividing the test into segments that evaluate multiple cells sharing common conductors, the system can identify whether defects are isolated to single cells or affect entire word lines/bit lines, enabling more accurate defect classification without requiring complete redesign of the test architecture.
3Measurement precision
If all memory cells are tested individually, then comprehensive defect identification is achieved, but test time increases reducing productivity
Solution Approach 1:
The patent implements a multi-functional test circuit that can operate in different modes: individual cell testing, word line aggregation, and bit line aggregation. This universal test structure can adaptively select the appropriate testing granularity based on the specific defect patterns being investigated, providing comprehensive defect identification capabilities while optimizing test time by avoiding redundant individual cell tests when aggregation suffices.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a first memory cell group, a first parallel bit test circuit configured to output a first fail signal based on each of the plurality of memory cells included in the first memory cell group being defective, and output a first pass signal based on at least one memory cell among the plurality of memory cells included in the first memory cell group being not defective, and a first latch circuit configured to selectively latch an output of the first parallel bit test circuit. The first latch circuit is configured to latch the output of the first parallel bit test circuit in response to the first parallel bit test circuit outputting the first pass signal The plurality of memory cells included in the first memory cell group are respective connected to different word lines, and connected to the same bit line.