3D Semiconductor Memory Device With Line Sharing Scheme
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Solution Overview
Problem
There is a need to increase the density of memory cells within a predetermined area in semiconductor memory devices while maintaining or improving electrical characteristics, as existing methods face limitations in reducing memory cell size and preventing deterioration of electrical performance.
Innovation Solution
A semiconductor memory device design that includes memory blocks stacked in layers over a substrate, with word lines coupled between memory blocks and shared bit lines, allowing for efficient read and program operations across multiple memory blocks, and utilizing specific circuitry to manage operating voltages and reduce interference between memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase the number of memory cells, then storage capacity increases, but electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking. Memory blocks are stacked in the vertical direction (MB0, MB1, MB2, MB3) with multiple bit lines extending vertically through the stack. This dimensional change allows increased memory cell density without reducing individual cell size, thereby maintaining electrical characteristics while increasing storage capacity.
2Quantity of substance
If more memory blocks are stacked vertically to increase density, then storage capacity increases, but interference between memory cells increases
Solution Approach 1:
The patent divides the memory array into multiple independently controllable memory blocks (MB0, MB1, MB2, MB3) stacked vertically. Each memory block can be selectively accessed through specific bit lines (BLA0-BLA3, BLB0-BLB3) and word lines (WL0-WL7). This segmentation allows operations in one memory block to be isolated from others, reducing interference while maintaining high density through vertical stacking.
Solution Approach 2:
The patent introduces selection lines (SGS0-SGS3 for source selection, SGD0-SGD3 for drain selection) as intermediary control elements between the bit lines and memory cells. These selection lines act as mediators that enable precise control of current flow paths, allowing selective access to specific memory cells within stacked blocks and preventing unwanted interference between adjacent memory blocks during read and program operations.
3Device complexity
If bit lines are shared between multiple memory blocks to reduce complexity, then device complexity decreases, but operational interference increases
Solution Approach 1:
The patent implements dynamic control of bit line sharing through time-multiplexed operation. Bit lines (BLA0-BLA3, BLB0-BLB3) are shared between adjacent memory blocks (e.g., BLA0 shared between MB0 and MB1), but selection lines dynamically enable or disable access to specific blocks during different operational phases. This dynamic control allows the same physical bit line to serve multiple blocks without causing interference, as only one block is active at any given time.
Data Source
AI summary
A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate and an operation circuit suitable for performing a read operation and a program loop to memory cells included in the memory blocks, wherein word lines of the memory blocks are coupled to each other and a pair of the memory blocks are arranged vertically adjacent to each other and share bit lines.