Semiconductor Memory Device Redundant Local Bit Line Defect Replacement
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Solution Overview
Problem
Semiconductor memory devices based on the hierarchical bit line scheme face performance degradation due to increased read time when addressing defects in local bit lines, and the complexity of error correction code circuits leads to increased chip area and current consumption.
Innovation Solution
The semiconductor memory device employs a configuration with redundant local bit lines that can replace defective local bit lines using row address comparison, eliminating the need for redundant global bit lines and simplifying the error correction code circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant global bit lines are added to address defects in local bit lines, then reliability is improved, but device complexity and chip area increase
Solution Approach 1:
The patent segments the bit line system into local bit lines (for normal operation) and redundant local bit lines (for defect replacement). Instead of creating redundant global bit lines, the invention divides the redundancy function into separate local segments that can be independently activated. This segmentation allows defect correction without increasing global bit line complexity.
Solution Approach 2:
The patent introduces a new dimension of control by adding row address comparison functionality that operates independently of the column address system. This allows defect detection and redundant bit line activation to occur in the row address dimension, bypassing the need for complex column-based error correction circuits.
2Reliability
If error correction code circuits are added to correct read data errors, then reliability is improved, but chip area and current consumption increase
Solution Approach 1:
The patent extracts the error correction function from complex ECC circuits and implements it through a simpler row address comparison mechanism. By taking out the core functionality of error detection and replacement and implementing it through address comparison rather than full ECC decoding, the chip area and current consumption are significantly reduced while maintaining reliability.
Solution Approach 2:
The patent uses a simple row address comparison circuit instead of expensive ECC circuits. The comparison circuit is much cheaper in terms of area and power, and the patent accepts that this simpler mechanism suffices for the error correction needs, replacing complex ECC with a more economical solution.
3Reliability
If redundant local bit lines are added with row address comparison, then reliability is improved, but device complexity increases
Solution Approach 1:
The row address comparison circuit serves multiple functions: it detects defects in local bit lines, activates redundant local bit lines when defects are detected, and integrates with the existing address multiplexing scheme. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while improving reliability.
Data Source
AI summary
A semiconductor memory device comprises: plurality of global bit lines; plurality of sense amplifier circuits each connected to corresponding one of the plurality of global bit lines; plurality of column selection lines each of which is connected to or disconnected from corresponding one of the plurality of sense amplifier circuits according to column address information; and plurality of local bit lines including first local bit line and second local bit line. The first local bit line is connected to or disconnected from corresponding one of the plurality of global bit lines according to first row address information different from column address information. The second local bit line replaces first local bit line when defect is present in first local bit line and is connected to or disconnected from corresponding global bit line according to second row address information different from column address information.