Semiconductor Memory Local and Global Data Circuits Parallel Operation
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Solution Overview
Problem
Next-generation memory apparatuses, such as PRAM, face challenges in achieving high operation speed while maintaining nonvolatile characteristics, as they require longer times for write and read operations compared to volatile DRAM, and struggle with random access speeds similar to flash memory.
Innovation Solution
A semiconductor memory apparatus is designed with a local data circuit in each memory bank for active write and read operations and a global data circuit in a peripheral region for buffer write and read operations, allowing for separate and parallel execution of these operations to enhance speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If next-generation memory apparatuses (PRAM, MRAM, ReRAM, FRAM) are used to achieve nonvolatile characteristics, then data retention without power supply is improved, but operation speed deteriorates compared to DRAM
Solution Approach 1:
The memory system is divided into multiple memory banks, each with its own local data circuit. This segmentation allows parallel operation of multiple banks, improving overall operation speed while maintaining nonvolatile characteristics through the use of phase-change memory cells in each bank.
Solution Approach 2:
A global data circuit is introduced as an intermediary between local data circuits and external devices. This global data circuit buffers and manages data transfer, enabling efficient coordination between the fast local operations and external interfaces, thereby improving overall system speed without compromising data retention.
2Speed
If local data circuits are added to each memory bank for active operations, then read/write speed is improved, but device complexity increases
Solution Approach 1:
The data circuit functionality is segmented into local data circuits at the memory bank level and a global data circuit at the system level. This segmentation distributes complexity across multiple simple local units rather than requiring one complex centralized circuit, improving read/write speed through localized processing while managing overall complexity.
Solution Approach 2:
The local data circuits in each memory bank are merged with the global data circuit through standardized interfaces. This merging allows the distributed local circuits to work together as a unified system, achieving high-speed operations without proportionally increasing overall device complexity through modular integration.
3Productivity
If global buffer array is separated from core region, then access efficiency is improved, but area of core region increases
Solution Approach 1:
The global buffer array is extracted from the core region and placed in the peripheral region. This extraction separates the buffer functionality from the memory storage area, improving access efficiency by allowing independent optimization of buffer operations without interfering with core memory operations, while the core region area is reduced.
Solution Approach 2:
The memory architecture transitions from a two-dimensional planar layout to a three-dimensional hierarchical structure, with the core region containing memory banks and the peripheral region containing the global buffer array. This dimensional reorganization improves access efficiency through spatial separation while managing area utilization more effectively.
Data Source
AI summary
A semiconductor memory apparatus may include a memory bank, a global buffer array, and an input and output circuit. The memory bank includes a local data circuit, and the global buffer array includes a global data circuit. The local data circuit is operably coupled to the global data circuit. The global buffer array may be operably coupled to the input and output circuit. The memory bank is disposed in a core region, and the global buffer array and the input and output circuit may be disposed in a peripheral region separated from the core region.