Semiconductor Device Manufacturing Method for Memory and Logic Units
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Solution Overview
Problem
The manufacturing of semiconductor devices, particularly memory devices, involves complex and time-consuming etching processes that increase costs due to the need for multiple masks and steps.
Innovation Solution
A method that minimizes etching processes by using a dielectric member as a mask and forming interconnect and control gate members from the same conductive material layer, allowing for the retention of a mask member in the gate structure and reducing the number of required masks and steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple etching processes with multiple masks are performed to manufacture memory device, then the gate structures of logic unit and memory unit can be formed, but the manufacturing time and cost increase
Solution Approach 1:
The patent combines the formation of control gate electrode and interconnect electrode into a single etching process. The conductive material layer is patterned to form both electrodes simultaneously, eliminating the need for separate etching processes and reducing manufacturing time while maintaining precise gate structure formation
Solution Approach 2:
The dielectric layer serves multiple functions: it acts as an etch mask during the formation of both control gate electrode and interconnect electrode, and subsequently becomes the gate insulating layer of the memory unit. This multi-functionality reduces the number of process steps required
2Manufacturing precision
If multiple etching processes with multiple masks are performed to manufacture memory device, then the gate structures of logic unit and memory unit can be formed, but the manufacturing cost increases
Solution Approach 1:
The patent merges the formation of control gate electrode and interconnect electrode into a single etching process using one mask layer, reducing material costs and process complexity while maintaining the required manufacturing precision for different gate structures
Solution Approach 2:
The dielectric layer is retained and reused as the gate insulating layer after serving as an etch mask, eliminating the need to deposit a separate gate insulating layer and reducing manufacturing costs
Data Source
AI summary
A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.