Semiconductor Memory Device With Logical Operation Control Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices face issues with providing sufficient differential voltage to sense amplifiers and compatibility with word line decoders, leading to potential bit errors and increased chip size when performing logical operations like AND and OR on stored data.
Innovation Solution
The semiconductor memory device incorporates a configuration with multiple memory cells and switching elements connected via bit lines and word lines, allowing for logical operations to be performed without an extra circuit by activating and deactivating word lines and sense amplifiers in a controlled manner, ensuring sufficient differential voltage and compatibility with existing DRAM circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor memory devices perform logical AND or OR operations on stored data, then data processing capability is improved, but the differential voltage supplied to sense amplifiers becomes smaller than required, causing bit errors
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines to a specific voltage level before performing logical operations. This ensures that when multiple memory cells are accessed simultaneously during AND or OR operations, the sense amplifiers receive sufficient differential voltage to reliably detect the results, preventing bit errors while maintaining data processing capability
Solution Approach 2:
The patent changes the voltage parameter by adjusting the bit line pre-charge voltage to a level that provides adequate differential voltage to sense amplifiers during logical operations. This parameter modification ensures reliable operation when multiple word lines are activated simultaneously, resolving the contradiction between data processing capability and bit error rate
2Adaptability or versatility
If a special word line decoder region is provided for logical AND and OR operations, then data processing functionality is improved, but chip size increases
Solution Approach 1:
The patent applies universality by designing the existing word line decoder circuit to perform both its traditional function of activating single word lines for normal memory operations and an additional function of simultaneously activating multiple word lines for logical AND and OR operations. This multi-functionality eliminates the need for a separate special decoder region, maintaining logical operation capability while avoiding chip size increase
Solution Approach 2:
The patent merges the logical operation control functionality into the existing word line decoder circuit by adding control logic that enables simultaneous activation of multiple word lines based on operation mode signals. This consolidation combines the functions of normal address decoding and logical operation control into a single circuit, preventing chip size expansion while providing required data processing functionality
Data Source
AI summary
A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.