Semiconductor Memory Control Circuit for Mode-Adaptive Data I/O

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Semiconductor devices require different control circuits for various data input/output modes, leading to inefficiencies and suboptimal performance due to the need for multiple circuits.

Innovation Solution

A semiconductor device design that includes a memory region selection circuit, column selection circuit, and data path selection circuit, capable of generating and activating select signals based on mode identification signals and operation modes to flexibly control data input/output operations using a single circuit, allowing for optimized performance across different modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different control circuits are implemented for various data input/output modes, then operational reliability is improved, but device complexity increases

Engineering Contradiction:
Improveoperational reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control circuit is designed to perform multiple functions by receiving mode identification signals that determine its operational behavior. The same control circuit generates different types of select signals (memory region select signals, column select signals, data path select signals) based on the mode identification signal, allowing it to adapt to various data input/output modes without requiring separate dedicated circuits for each mode.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple control circuits are used for different modes, then operational stability is improved, but area consumption increases

Engineering Contradiction:
Improveoperational stabilityVSAvoidarea consumption
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Multiple control functions that would traditionally require separate control circuits are merged into a single control circuit. This circuit integrates the generation of memory region select signals, column select signals, and data path select signals, all controlled by a unified mode identification signal, thereby reducing the total area occupied by control logic while maintaining operational stability across different modes.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If separate control circuits are implemented for various modes, then mode-specific performance is optimized, but power consumption increases

Engineering Contradiction:
Improvemode-specific performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The control circuit operates dynamically by changing its behavior based on the mode identification signal. Instead of having multiple static control circuits always active, a single control circuit dynamically adjusts its output signal generation according to the current operating mode, thereby maintaining mode-specific performance optimization while reducing overall power consumption by keeping only one control circuit active.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10714161B2Semiconductor device
Publication Date: 2020.07.14 SK HYNIX INC
  • US10714161B2 patent drawing
  • US10714161B2 patent drawing
  • US10714161B2 patent drawing

AI summary

A semiconductor device includes: a memory region selection circuit for generating memory region select signals based on a memory region address signal and a mode identification signal, and activating one or more memory region select signals among memory region select signals during a first mode, or activating two or more memory region select signals among the memory region select signals during a second mode; a column selection circuit for generating column select signals based on a column address signal and the mode identification signal, and changing the column select signals during the first mode, or retaining the column select signals during the second mode; and memory regions of which one or more memory regions are accessed during the first mode or two or more memory regions are accessed during the second mode, based on the memory region select signals and the column select signals.