3D Semiconductor Memory Device Impurity Outgassing Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The economic limitation of increasing integration in two-dimensional memory semiconductor devices due to the high cost of equipment required for forming fine patterns, which hinders the advancement of memory density and reliability.
Innovation Solution
A semiconductor memory device with a stack of gate electrodes and insulating layers alternately stacked on a substrate, featuring cell and dummy channel structures that penetrate the stack, allowing for increased integration density and reliability through a method that includes forming semiconductor patterns by selective epitaxial growth, with the use of a mold insulating layer and dummy channel structures to manage impurity outgassing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective epitaxial growth is used to form semiconductor patterns, then manufacturing precision is improved, but impurity outgassing occurs during the process
Solution Approach 1:
A mold insulating layer is introduced as an intermediary between the substrate and the semiconductor pattern formation process. This layer serves as a barrier that prevents impurities generated during selective epitaxial growth from outgassing and contaminating the semiconductor patterns, thereby maintaining manufacturing precision while addressing the harmful outgassing effect
Solution Approach 2:
The harmful impurity outgassing is extracted and isolated from the semiconductor pattern formation process by containing it within the mold insulating layer structure. This separation allows the epitaxial growth to proceed with high precision while the impurities are confined and prevented from affecting the semiconductor patterns
2Quantity of substance
If three-dimensional stacked structure is implemented, then integration density is improved, but device complexity increases
Solution Approach 1:
The invention transitions from two-dimensional planar memory structures to three-dimensional stacked structures by vertically stacking multiple insulating layers and electrode patterns. This dimensional change enables significantly higher integration density as memory cells are arranged in multiple layers rather than a single plane
Solution Approach 2:
The three-dimensional stacked structure is segmented into multiple functional layers including first and second insulating layers, first and second electrode patterns, and semiconductor patterns. Each layer serves specific functions and can be independently formed and controlled, which manages the overall device complexity through modular construction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances integration density and reliability of semiconductor memory devices by reducing the impact of impurity outgassing on semiconductor pattern growth, resulting in improved memory performance and cost-effectiveness.
Implementation Method 1
forming semiconductor patterns by selective epitaxial growth
Data Source
AI summary
A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.