Semiconductor Memory Multi-Page Read Reliability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor memory devices face challenges in maintaining data reliability due to changes in threshold voltages of memory cells over time, leading to read errors and operational instability, especially in three-dimensional memory cell arrays.

Innovation Solution

The semiconductor memory device employs a multi-page read operation by simultaneously selecting and applying a read voltage to multiple word lines coupled to a page group, ensuring stable data retrieval even when threshold voltages decrease, and utilizes a content addressable memory block to manage operational parameters and retry data, enhancing operational reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional single-page read operation is performed on three-dimensional memory cells, then the device complexity is low, but the data read reliability deteriorates due to threshold voltage changes over time

Engineering Contradiction:
Improvedata read reliabilityVSAvoidread operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory block is divided into multiple page groups, where each page group contains multiple physical pages that share common word lines. This segmentation allows the system to selectively activate multiple pages simultaneously through a unified read operation, improving reliability by reading from multiple threshold voltage profiles while maintaining manageable device complexity through structured organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent pre-organizes memory pages into page groups with shared word lines before operation. This preliminary structuring enables the peripheral circuit to perform multi-page reads by simply selecting the appropriate page group and applying a single read voltage to shared word lines, avoiding the complexity of individually managing multiple read operations while ensuring reliable data retrieval across varying threshold voltages.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple word lines are simultaneously selected for multi-page read operation, then the data read reliability improves, but the use of energy increases

Engineering Contradiction:
Improvedata retrieval stabilityVSAvoidenergy consumption during read operation
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Multiple physical pages that share common word lines are merged into a single page group. When a read operation is performed on this page group, the same read voltage is simultaneously applied to all shared word lines, enabling parallel data retrieval from multiple pages. This merging approach improves data retrieval stability by accessing multiple pages in one operation while minimizing energy consumption by using a unified voltage application rather than separate operations for each page.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If a content addressable memory block is added to manage operational parameters, then the operational reliability improves, but the device complexity increases

Engineering Contradiction:
Improveoperational reliabilityVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The content addressable memory block serves multiple functions: it stores operational parameters for controlling memory cell operations, maintains retry data for error correction, and provides information for adaptive read voltage adjustment. By consolidating these diverse functions into a single memory structure, the patent improves operational reliability without proportionally increasing device complexity, as the same hardware resource supports multiple critical operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10559363B2Semiconductor memory device and method related to operating the semiconductor memory device
Publication Date: 2020.02.11 SK HYNIX INC
  • US10559363B2 patent drawing
  • US10559363B2 patent drawing
  • US10559363B2 patent drawing

AI summary

The semiconductor memory device may include a memory cell array and a peripheral circuit. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a multi-page read operation on a selected memory block among the plurality of memory blocks. The peripheral circuit may select a first word line and a second word line, which are coupled to the selected memory block, and perform the multi-page read operation on the first and second word lines.