Semiconductor Memory Multi-Plane Read Architecture
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in reading multiple-bit data due to the need for multiple read operations across different memory cell arrays, leading to increased power consumption and reduced operation speed.
Innovation Solution
A semiconductor memory system that employs multiple memory cell arrays with distinct threshold voltage distributions, allowing for simultaneous read operations across planes using specific read voltages, thereby reducing the number of read operations required and optimizing data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple read operations are performed across different memory cell arrays to read multi-bit data, then data storage capacity is maintained, but power consumption increases and operation speed decreases
Solution Approach 1:
The patent combines multiple memory cell arrays (first and second memory cell arrays) into a unified read operation system. By configuring both arrays to share common bit lines and control circuits, and by applying the same read voltage to both arrays simultaneously, the system can retrieve multi-bit data (e.g., 2-bit data) from both arrays in a single read operation, thereby reducing power consumption and improving read speed compared to performing separate read operations.
Solution Approach 2:
The patent implements a universal read voltage generation circuit that can simultaneously control multiple memory cell arrays with different threshold voltage distributions. The read voltage is designed to be applicable to both the first memory cell array (with first threshold voltage distribution) and the second memory cell array (with second threshold voltage distribution), enabling both arrays to function together in a single read operation for enhanced data retrieval efficiency.
2Productivity
If multiple read operations are performed across different memory cell arrays to read multi-bit data, then data storage capacity is maintained, but the number of read operations increases
Solution Approach 1:
The patent merges the read operations of multiple memory cell arrays by configuring them to share common bit lines and control circuits. This allows simultaneous reading from both the first and second memory cell arrays in a single operation cycle, eliminating the need for sequential read operations and thereby reducing the total time required to retrieve multi-bit data.
Solution Approach 2:
The patent enables continuous and simultaneous read operations across multiple memory cell arrays by applying the same read voltage to both arrays at the same time. This continuous parallel operation eliminates idle time between sequential reads, maintaining productive action throughout the data retrieval process and significantly reducing the overall read operation time.
Data Source
AI summary
A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.