3D Semiconductor Memory Device Parasitic Capacitance Reduction
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in reducing parasitic capacitance, which affects operation speed and efficiency due to the complex structure and voltage application during data erasure, writing, and reading processes.
Innovation Solution
The semiconductor memory device incorporates a semiconductor substrate with an n-type semiconductor region facing the end portion of the memory semiconductor layer, reducing capacitance by isolating the memory layer from the substrate and optimizing the configuration of columnar and connecting portions to minimize parasitic capacitance, thereby enhancing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally disposed to achieve large capacity and high integration, then storage capacity increases, but parasitic capacitance increases affecting operation speed
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking, where memory cells are disposed in multiple layers above the substrate. This dimensional change allows significantly increased storage capacity within the same footprint while managing parasitic capacitance through vertical isolation structures and optimized layer spacing.
Solution Approach 2:
The memory device is segmented into multiple independent memory cell layers stacked vertically, with each layer containing complete memory cells including semiconductor layers, charge accumulating layers, and control gate electrodes. This segmentation allows independent operation of each layer, reducing inter-layer parasitic capacitance while maintaining high density.
2Productivity
If complex three-dimensional structure is implemented for high integration, then device density increases, but parasitic capacitance increases reducing efficiency
Solution Approach 1:
Insulating layers are introduced as intermediary elements between adjacent memory cell layers and between conductive components. These insulating layers act as mediators that electrically isolate conductive elements while maintaining physical proximity for high density, thereby reducing parasitic capacitance between adjacent structures.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the three-dimensional memory device. Specifically, insulating materials are placed in critical capacitance-reduction zones, while conductive materials are optimized for signal transmission paths. This local optimization of material quality minimizes parasitic capacitance in high-density regions.
Data Source
AI summary
According to the embodiments, the semiconductor memory device includes a semiconductor substrate, a first conducting layer, a semiconductor layer, a plurality of second conducting layer, and an electric charge accumulating layer. The first conducting layer is disposed on the semiconductor substrate via an insulating layer. The semiconductor layer is disposed on the first conducting layer and extends in a first direction above the semiconductor substrate. The plurality of the second conducting layers extends in a second direction intersecting with the first direction, and is laminated along the first direction via an insulating layer, and is disposed on the first conducting layer. The electric charge accumulating layer is disposed between the semiconductor layer and the plurality of second conducting layer. The semiconductor substrate includes an n type semiconductor region facing an end portion of the semiconductor layer.