Semiconductor Memory Device Noise Balancing via Capacitive Element
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Solution Overview
Problem
As semiconductor memory devices miniaturize, increased parasitic capacitance between adjacent bit lines and word lines leads to noise interference, where noise on one bit line can affect adjacent lines, compromising data read operations.
Innovation Solution
Incorporating a capacitive element between specific nodes in the power supply circuits to balance noise transmission between bit lines and word lines, ensuring equal noise voltage is applied to both, thereby offsetting noise and maintaining accurate data detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the interval between adjacent bit lines is reduced to miniaturize the device, then the device size is reduced, but the parasitic capacitance between bit lines increases causing noise interference
Solution Approach 1:
The patent applies preliminary anti-action by introducing a capacitive element that proactively counteracts noise interference before it affects data reading. The capacitive element is configured to generate a noise counter-voltage that opposes and cancels the parasitic capacitance-induced noise, thereby preventing noise from corrupting the read operation even as bit lines are closely spaced for miniaturization
Solution Approach 2:
The capacitive element serves as an intermediary component between the bit line and the noise source (parasitic capacitance). It mediates the noise interference by coupling to the bit line and introducing a counteracting capacitive effect, thereby isolating the data reading process from the harmful parasitic capacitance while maintaining the miniaturized structure
2Volume of moving object
If the interval between adjacent word lines is reduced to miniaturize the device, then the device size is reduced, but the parasitic capacitance between word lines increases causing noise interference
Solution Approach 1:
The capacitive element provides preliminary anti-action by preemptively counteracting the noise from parasitic capacitance between word lines. It generates a counter-voltage that opposes the noise before it can interfere with the selected word line operation, enabling miniaturization while maintaining signal integrity
Solution Approach 2:
The capacitive element acts as an intermediary between the word line system and the parasitic capacitance noise. It mediates the interaction by introducing a beneficial capacitive coupling that counterbalances the harmful parasitic effects, allowing close spacing of word lines without sacrificing reliability
3Reliability
If a capacitive element is added to counteract noise, then noise interference is reduced, but the device complexity increases
Solution Approach 1:
The capacitive element is designed with multi-functionality, serving both as a noise counteraction mechanism and as an integral part of the power supply circuit structure. By making the capacitive element a shared component that serves multiple purposes (noise cancellation and power distribution support), the patent reduces the need for additional dedicated noise cancellation components, thereby limiting the increase in device complexity while maintaining improved noise resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise interference by simultaneously transmitting equal noise voltages to bit lines and word lines, ensuring accurate data detection and shortening data detection time, even in the presence of parasitic capacitance.
Implementation Method 1
A capacitive element is formed or connected between a first node that is between the second power supply circuit and the first decoder and a second node that is between the third power supply circuit and the second decoder
Data Source
AI summary
A semiconductor memory device includes a memory cell array with bit lines and word lines connected thereto. A first power supply circuit generates a selected bit line voltage. A second power supply circuit generates a non-selected bit line voltage. A third power supply circuit generates a selected word line voltage. A fourth power supply circuit generates a non-selected word line voltage. A first decoder connects the selected bit line to the first power supply circuit and connects the non-selected bit line to the second power supply circuit. A second decoder connects the selected word line to the third power supply circuit and connects the non-selected word line to the fourth power supply circuit. A capacitive element is between a first node that is between the second power supply circuit and the first decoder and a second node that is between the third power supply circuit and the second decoder.