Semiconductor Memory Device Non-Standard Density Configuration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods face challenges in increasing the density of dynamic random access memory (DRAM) devices beyond traditional power-of-2 capacities, limiting further refinement and efficiency in memory cell density.
Innovation Solution
The integration of multiple memory regions on a single chip with non-standard densities, such as 2^M+2^N+2^O, where M, N, and O are integers, allowing for a sum of memory capacities that cannot be expressed as a single power of 2, along with a peripheral region for controlling read/write operations, enables a more efficient use of chip input/output terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional methods are used to increase DRAM density by increasing row addresses, column addresses, and bank addresses, then memory capacity increases in powers of 2, but the ability to achieve non-standard densities is limited
Solution Approach 1:
The memory device is divided into multiple memory regions (first memory region, second memory region, etc.) with different capacities (2^M bits, 2^N bits, 2^O bits). Each region can be independently accessed and configured, allowing the total capacity to be any sum of powers of 2 rather than requiring the entire device to operate at a single power-of-2 density level.
Solution Approach 2:
The peripheral region dynamically selects which memory region to access based on address and command signals. The I/O connecting block can connect different input/output terminals to chip input/output terminals based on which memory region is being accessed, enabling flexible configuration of the active memory capacity.
2Adaptability or versatility
If multiple memory regions with different capacities are integrated on a single chip, then non-standard densities are achieved, but the control complexity increases
Solution Approach 1:
The peripheral region serves multiple functions: it controls read/write operations for different memory regions, manages I/O terminal connections, and handles address decoding for multiple capacity configurations. The I/O connecting block provides universal connectivity, able to connect any memory region's input/output terminals to the chip's external I/O terminals based on the active memory region.
3Productivity
If standard power-of-2 density configurations are used, then manufacturing and addressing are simplified, but system performance and power efficiency are compromised
Solution Approach 1:
Different memory regions have different local qualities in terms of capacity (2^M, 2^N, 2^O bits). This allows the memory device to be optimized for specific applications by activating only the required capacity, improving power efficiency and system performance by avoiding the overhead of larger power-of-2 configurations when smaller capacities suffice.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2^K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.