Semiconductor Memory Open Bitline Structure Noise Management
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Solution Overview
Problem
Conventional semiconductor memory devices with folded bitline structures face limitations in reducing memory cell size, hindering increased integration density, and struggle with common mode noise removal.
Innovation Solution
The semiconductor memory device employs an open bitline structure with separate memory-cell array regions and sense-circuit regions, utilizing P-type and N-type sense amplifiers and equalizers to amplify voltage differences between bitlines and complementary bitlines, and column-selection transistors to couple lines to I/O lines, optimizing layout and sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If folded bitline structure is used, then common mode noise can be easily removed by differential amplification, but memory cell size reduction is limited and integration density cannot be increased
Solution Approach 1:
The memory device is divided into separate first and second memory cell array regions with their respective bitline pairs, allowing independent optimization of each region while maintaining overall system functionality
Solution Approach 2:
Sense circuit regions are introduced as intermediary components between memory cell array regions, providing noise filtering and signal amplification functions that enable the transition from folded to open bitline structure while maintaining noise immunity
2Area of moving object
If open bitline structure is used, then integration density is increased, but common mode noise management becomes more difficult
Solution Approach 1:
The sense amplifiers are configured to amplify the difference between bitline and complementary bitline voltages, converting the harmful common mode noise into a differential signal that can be selectively amplified while rejecting the common mode component
Solution Approach 2:
Different regions of the memory device have specialized functions: memory cell array regions for data storage, sense circuit regions for noise filtering and signal amplification, and equalizer circuit regions for voltage balancing, allowing each region to be optimized for its specific function
3Measurement precision
If sense circuit regions are placed between memory cell array regions, then sensing functionality is improved, but device complexity increases
Solution Approach 1:
The sense circuit regions serve multiple functions simultaneously: they act as differential amplifiers to amplify voltage differences between bitlines, as common mode noise filters to reject unwanted signals, and as signal buffers to isolate memory cell arrays from I/O circuits
Solution Approach 2:
Multiple circuit functions (amplification, filtering, buffering) are merged into single sense circuit region blocks, reducing the overall number of discrete components and simplifying the device structure while maintaining enhanced sensing capabilities
Data Source
AI summary
A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.