Semiconductor Memory Device with Oxide Semiconductor Transistor
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Solution Overview
Problem
Semiconductor memory devices face limitations in data retention without power supply, high cost due to complex circuits, and electrostatic breakdown issues, particularly in flash memory devices that require frequent writing operations and high voltage for charge retention.
Innovation Solution
A semiconductor memory device design incorporating a bit line, word line, source line, common wiring, and transistors with an oxide semiconductor, featuring a netlike conductive film that functions as both a capacitor electrode and guard ring to prevent electrostatic breakdown, allowing for long-term data retention and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If flash memory is used for non-volatile storage, then data retention time is extremely long and refresh operation is not needed, but the gate insulating layer deteriorates by tunneling current after a predetermined number of writing operations
Solution Approach 1:
The patent divides the memory system into two distinct parts: volatile memory for frequent write operations and non-volatile memory for data retention. This segmentation allows each part to operate within its optimal performance range, preventing the gate insulating layer deterioration issue in flash memory while maintaining long data retention capability.
Solution Approach 2:
The patent introduces a transfer mechanism as an intermediary between volatile and non-volatile memory regions. Data is transferred from the volatile region (where writes occur) to the non-volatile region (where data is retained), protecting the flash memory's gate insulating layer from excessive tunneling current damage while maintaining data retention functionality.
2Adaptability or versatility
If volatile memory (DRAM/SRAM) is used, then frequent rewrite operations are possible, but data is lost when power supply stops and refresh operation is needed
Solution Approach 1:
The memory system is segmented into volatile and non-volatile regions, allowing the volatile region to handle frequent rewrite operations while the non-volatile region ensures data persistence. This dual-structure resolves the contradiction between rewrite capability and data retention time.
Solution Approach 2:
The system performs preliminary transfer of data from the volatile memory region to the non-volatile memory region before power loss occurs. This preliminary action ensures that data is preserved even though the volatile memory cannot retain data without power.
3Duration of action of stationary object
If floating gate is used to retain charge, then data retention is achieved, but high voltage is necessary and write/erase operations are slow
Solution Approach 1:
The patent separates the functions of fast writing (in volatile memory) and long-term retention (in non-volatile memory). This segmentation allows the system to achieve both fast operation speeds and long data retention times by utilizing the strengths of each memory type in their respective regions.
4Reliability
If complex circuits are used to equalize writing operations, then flash memory lifetime is extended, but cost per storage capacity becomes high
Solution Approach 1:
Instead of using complex peripheral circuits to manage wear in flash memory, the patent segments the memory into volatile and non-volatile regions. This simpler architectural approach extends flash memory lifetime by reducing write operations to the non-volatile region, achieving reliability improvement without increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable, high-yield semiconductor memory devices with extended data retention and reduced power consumption by minimizing off-state current and electrostatic breakdown, while maintaining high storage capacity per unit area.
Implementation Method 1
a third transistor including an oxide semiconductor... since charge of a capacitor is lost instantaneously after information is read out, rewriting needs to be performed every time information is read out. In addition, when a transistor included in the DRAM is off, charge is lost due to leakage current (off-state current) between a source and a drain
Implementation Method 2
a capacitor connected to the transistor... charge is stored in a capacitor
Implementation Method 3
a gate insulating layer included in the semiconductor memory device deteriorates by tunneling current generated in writing
Data Source
AI summary
In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring.