Semiconductor Memory Pads With Differential Widths
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, misalignment between channel layers and bit lines can occur due to manufacturing processes, leading to leakage current and malfunction, as the channel layer may be misaligned with the bit line, causing bending of cell plugs and contact plugs which exacerbates misalignment.
Innovation Solution
The semiconductor memory device incorporates pads with differential-width structures that adjust their width based on the bending tendency of channel layers, effectively compensating for misalignment by increasing width towards the word line contact region, thereby stabilizing the coupling between channel layers and contact plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If channel layers are formed in vertical stacks for high integration, then storage capacity is improved, but misalignment between channel layers and bit lines occurs during manufacturing
Solution Approach 1:
The pad structure is designed with non-uniform width where the first portion has a greater width than the second portion. This local variation in geometry compensates for the bending of channel layers, ensuring that the pad maintains proper alignment with the bit line even when the channel layer position shifts during manufacturing.
Solution Approach 2:
The pad width is pre-adjusted during the design and fabrication stage to anticipate and compensate for the expected bending of channel layers. By incorporating the greater width portion at the first portion of the pad before the actual misalignment occurs, the design proactively prevents misalignment issues during subsequent manufacturing processes.
2Reliability
If channel layers are misaligned with bit lines, then leakage current increases, but device reliability deteriorates
Solution Approach 1:
The pad structure is designed with non-uniform width where the first portion has a greater width than the second portion. This local variation in geometry compensates for the bending of channel layers, ensuring that the pad maintains proper alignment with the bit line even when the channel layer position shifts during manufacturing.
Solution Approach 2:
The pad width is pre-adjusted during the design and fabrication stage to anticipate and compensate for the expected bending of channel layers. By incorporating the greater width portion at the first portion of the pad before the actual misalignment occurs, the design proactively prevents misalignment issues during subsequent manufacturing processes.
3Stability of the object's composition
If pad width is increased to compensate for bending, then alignment stability is improved, but manufacturing complexity increases
Solution Approach 1:
The pad structure is designed with non-uniform width where the first portion has a greater width than the second portion. This local variation in geometry compensates for the bending of channel layers, ensuring that the pad maintains proper alignment with the bit line even when the channel layer position shifts during manufacturing.
Solution Approach 2:
The pad width is pre-adjusted during the design and fabrication stage to anticipate and compensate for the expected bending of channel layers. By incorporating the greater width portion at the first portion of the pad before the actual misalignment occurs, the design proactively prevents misalignment issues during subsequent manufacturing processes.
Data Source
AI summary
Provided herein is a semiconductor memory device. The semiconductor memory device may include channel layers protruding away from a substrate. The semiconductor memory device may include a plurality of pads respectively coupled to the channel layers. The widths of the pads may or may not be increased depending on a bending of the channel layers.