Semiconductor Memory Page-Level Error Correction
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Solution Overview
Problem
NOR flash memory experiences decreased data reliability and slower access speeds due to the need for error correction across larger block units, which is not efficiently addressed by existing error correction methods designed for NAND flash memory.
Innovation Solution
A semiconductor memory system and data writing method that applies error-correction encoding only to specific page data pieces within a block unit, using a write page address detector to identify and incorporate write data into designated page data, and then applies error correction and writing voltage to memory cells based on encoded write data pieces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is applied to all page data in a block unit, then data reliability is improved, but access time increases
Solution Approach 1:
The patent segments the block unit into individual page data units and applies error correction only to those pages that actually contain write data. This is achieved by detecting which pages have write data through address analysis, then selectively applying ECC encoding only to those specific pages rather than processing the entire block. This segmentation approach maintains data reliability for modified pages while reducing unnecessary processing time for pages without changes.
Solution Approach 2:
The patent applies partial action by performing error correction only on the subset of page data that actually contains write data, rather than applying it to all pages in the block. The system determines which pages require ECC processing through address detection, and only those pages are subjected to the time-consuming encoding process. This partial application of ECC maintains sufficient error correction coverage while significantly reducing processing time compared to full-block ECC.
2Adaptability or versatility
If write data pieces are distributed over multiple page data, then flexibility is improved, but error correction complexity increases
Solution Approach 1:
The patent performs preliminary action by detecting and identifying which pages contain write data before applying error correction. Through address analysis of the write data pieces, the system pre-determines the target pages that will receive ECC encoding. This preliminary identification step organizes the complex task of distributed error correction by first mapping which pages need processing, thereby simplifying the subsequent ECC application process even when data is scattered across multiple pages.
Solution Approach 2:
The patent introduces an intermediary approach by using address detection and page identification as a mediating step between the write data pieces and the ECC encoding process. The system analyzes write data addresses to determine target pages, creating an intermediate mapping layer that connects scattered write data pieces to their corresponding pages. This intermediary mechanism simplifies the complexity of distributing ECC across multiple pages by providing a clear organizational structure through address-based page identification.
Data Source
AI summary
On the basis of data addresses indicative of write bit positions of each of the write data pieces in each of blocks, write page addresses indicative of pages having each of the write data pieces written thereto in each of the blocks are detected. At least one write data piece is incorporated into each of the page data pieces indicated by the write page addresses among k page data pieces corresponding to the k pages, the page data pieces having the write data pieces incorporated therein are used as page data pieces, and an error-correction encoding process is applied to each of the write page data pieces to obtain encoded write data pieces. Then, a voltage based on the encoded write data pieces is applied to each of the memory cells belonging to the pages indicated by the write page addresses.