Semiconductor Memory Parallel Access Bus Architecture
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Solution Overview
Problem
Existing semiconductor memory systems face inefficiencies due to the inability to access ROM and RAM regions in parallel, leading to increased wait cycles and reduced processing efficiency, as they require separate memory devices with fixed storage capacities, increasing design and production costs.
Innovation Solution
A semiconductor memory device with multiple memory regions, each with separate buses and port connection control circuits, allowing parallel access to different attributes of information, and a transfer control circuit for efficient data transfer between memory regions, enabling flexible storage capacity optimization and reduced wait cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate memory devices (ROM and RAM) are used with fixed storage capacities, then the storage capacities can be optimized for individual purposes, but the design and production costs increase
Solution Approach 1:
The patent combines ROM and RAM regions into a single semiconductor memory device, allowing both memory types to coexist in one integrated structure. This merging approach enables flexible capacity allocation for different applications while reducing the number of separate devices needed, thereby lowering design and production costs associated with multiple discrete memory components
Solution Approach 2:
The semiconductor memory device provides universal functionality by incorporating both ROM (for fixed information storage) and RAM (for working memory) in a single device. This multi-functional design allows the same device to serve multiple purposes - storing boot programs, control data, application programs, and processed data - eliminating the need for separate specialized memory devices
2Device complexity
If ROM and RAM regions are accessed via a common data bus, then the memory architecture is simplified, but parallel access is prevented causing increased wait cycles
Solution Approach 1:
The patent segments the data bus into separate instruction bus and data bus channels, allowing simultaneous parallel access to ROM (for instructions) and RAM (for data). This segmentation enables the processor to fetch instructions and access data at the same time through different bus pathways, eliminating wait cycles while maintaining architectural simplicity through structured bus organization
Solution Approach 2:
The patent adds a temporal dimension to bus access by enabling simultaneous operation across multiple bus dimensions - the instruction bus handles ROM access while the data bus handles RAM access in parallel. This dimensional approach to bus organization allows overlapping operations that would be sequential in a single-bus architecture, thereby improving processing throughput without complicating the basic memory architecture
3Reliability
If instruction fetch is performed after data access completion, then bus conflicts are avoided, but wait cycles increase reducing instruction execution speed
Solution Approach 1:
The patent implements preliminary action by allowing instruction fetch to occur simultaneously with data access through separate bus pathways. The instruction bus is activated in advance to fetch opcodes from ROM while the data bus handles data transactions with RAM, eliminating the sequential dependency that would otherwise require wait cycles. This preliminary parallel activation of both buses resolves the time loss without compromising bus access control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables fast and efficient operational processing by allowing parallel access to ROM and RAM regions, reducing wait cycles and design costs, while optimizing storage capacity for various applications.
Implementation Method 1
a Magnetic Random Access Memory (MRAM) in which an element such as a TMR (Tunneling MagnetoResistance) element or a MTJ (Magnetic Tunneling Junction) element utilizing a magnetoresistance effect, are employed for a memory element
Data Source
AI summary
A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.