Semiconductor Memory Parallel Data Transfer via Segmented Buses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in data transfer operations due to a large number of sense amplifier units and latch circuits being coupled via a single bus, leading to sequential data transfer and increased time as the number of units increases, which affects the speed and miniaturization of the device.
Innovation Solution
The semiconductor memory device employs a configuration where fewer sense amplifier units are coupled to each of multiple buses, allowing parallel data transfer operations between the sense amplifier module and the data register, and utilizes interconnects and buses formed in specific layers to reduce resistance and enhance data transfer speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bus is used to couple all sense amplifier units and latch circuits, then the device structure is simple, but the data transfer speed decreases and transfer time increases as the number of units increases
Solution Approach 1:
The patent divides the single bus into multiple separate buses (first data line and second data line), coupling different groups of sense amplifier units and latch circuits to different buses. This segmentation allows parallel data transfer operations, increasing data transfer speed while maintaining structural simplicity through systematic organization.
2Device complexity
If a single bus is used to couple all sense amplifier units and latch circuits, then the device structure is simple, but the data transfer time increases as the number of units increases
Solution Approach 1:
The patent divides the single bus into multiple separate buses (first data line and second data line), coupling different groups of sense amplifier units and latch circuits to different buses. This segmentation allows parallel data transfer operations, reducing data transfer time by enabling simultaneous transfers across multiple buses.
Solution Approach 2:
The patent enables continuous parallel data transfer operations by maintaining multiple active data transfer paths simultaneously. Different groups of sense amplifier units can transfer data to different latch circuits at the same time through separate buses, maximizing the utilization of data transfer resources and reducing overall transfer time.
3Quantity of substance
If more sense amplifier units are added to increase device capacity, then the storage capacity increases, but the data transfer efficiency decreases due to sequential transfer through a single bus
Solution Approach 1:
The patent divides the single bus into multiple separate buses (first data line and second data line), coupling different groups of sense amplifier units and latch circuits to different buses. This segmentation allows parallel data transfer operations, increasing data transfer efficiency while supporting a larger number of sense amplifier units and latch circuits.
4Speed
If the bus width is increased to improve data transfer speed, then the data transfer speed increases, but the device area and resistance increase
Solution Approach 1:
The patent divides the single wide bus into multiple narrower separate buses (first data line and second data line). This segmentation achieves high data transfer speed through parallel transfers on multiple narrower lines, reducing the area and resistance of each individual bus while maintaining or improving overall data transfer performance.
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a first memory cell, a first interconnect, a first sense amplifier, a second interconnect, and a first latch circuit. The first interconnect is coupled to the first memory cell and extends in a first direction in a first interconnect layer. The first sense amplifier is coupled to the first interconnect. The second interconnect is coupled to the first sense amplifier and extends in the first direction in the first interconnect layer. The first latch circuit is coupled to the second interconnect. An end surface of the first interconnect on a side facing the first direction is opposed to an end surface of the second interconnect on a side facing a direction opposite to the first direction.