Semiconductor Memory Parameter Storage for Clock Alignment
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Solution Overview
Problem
Existing semiconductor memory systems require extensive tuning and testing to optimize clock-based parameters, such as tDQSCK, due to variations in process, voltage, and temperature environments, leading to inefficiencies in data signal and data strobe signal alignment.
Innovation Solution
A semiconductor memory system that includes a storage unit to store and output clock-based parameter information in response to test mode signals, allowing a memory controller to adjust interface values based on this information without additional training, utilizing a delay locked loop to generate data strobe signals and employing a register or e-fuse circuit for parameter storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If extensive tuning and testing are performed to optimize clock-based parameters, then parameter optimization is improved, but development time and complexity increase
Solution Approach 1:
The patent applies preliminary action by performing tuning and testing during the manufacturing process and storing the optimized parameter information in non-volatile memory (such as e-fuses or registers). This allows the memory device to provide pre-optimized parameter data to the memory controller without requiring extensive re-testing during system initialization, thereby reducing development time while maintaining parameter optimization.
2Manufacturing precision
If extensive tuning and testing are performed to optimize clock-based parameters, then parameter optimization is improved, but device complexity increases
Solution Approach 1:
The patent extracts the complex tuning and testing processes from the normal operation flow by performing them during manufacturing and storing the results in non-volatile memory. The memory controller simply reads the pre-optimized parameter information during initialization, separating the complex optimization task from the device operation complexity and reducing the testing burden during system deployment.
3Manufacturing precision
If additional training works are performed to optimize interface information, then interface optimization is improved, but operation time increases
Solution Approach 1:
The patent applies preliminary action by completing interface parameter optimization during the manufacturing process and storing the results in non-volatile memory. The memory controller then uses this pre-optimized interface information during system initialization without requiring additional training works, thereby optimizing the interface while avoiding time-consuming operations during system operation.
4Manufacturing precision
If clock-based parameter information is stored and transmitted, then interface optimization is improved, but device complexity increases
Solution Approach 1:
The patent extracts the parameter storage and transmission functions from the main device operation by using dedicated non-volatile memory elements (such as e-fuses or registers) that are specifically designed for storing calibration data. This separates the optimization function from the main memory array, reducing the complexity of the storage and transmission mechanisms while maintaining interface optimization.
Data Source
AI summary
A memory system includes a semiconductor memory including a storage unit configured to store parameter information in response to a test mode signal and to output the stored parameter information in response to a parameter request signal, and a memory controller configured to provide the parameter request signal to the semiconductor memory and receive the parameter information from the semiconductor memory device.