3D Semiconductor Memory Tiers with Integrated Peripheral Circuits
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Solution Overview
Problem
The challenge in semiconductor constructions is to increase memory cell density without significant additional processing steps, while maintaining the complexity of peripheral circuits in three-dimensional devices.
Innovation Solution
Fabricating portions of three-dimensional transistors and memory cells in the same tier of semiconductor material, where access lines and decoder transistors are integrated within the same tiers as memory cells, allowing for increased density without additional processing events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased in three-dimensional semiconductor devices, then storage capacity improves, but peripheral circuit functionality deteriorates due to space constraints
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking, allowing memory cells and peripheral circuits to coexist in different spatial tiers. Memory cells are positioned in upper tiers while peripheral circuits occupy lower tiers, enabling both high density and full circuit functionality without mutual interference.
Solution Approach 2:
The semiconductor device is divided into distinct functional tiers: memory cell tiers and peripheral circuit tiers. This segmentation allows each region to be optimized independently for its specific function while maintaining overall system integration and functionality.
2Device complexity
If peripheral circuits are integrated in the same tiers as memory cells, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
By separating memory cells and peripheral circuits into different vertical tiers, the patent reduces in-plane complexity while managing manufacturing precision through vertical stacking techniques. The tiered structure allows for standardized fabrication processes that maintain precision requirements at acceptable levels.
Data Source
AI summary
Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.