Semiconductor Memory Device Pillar Capacitor Step Formation
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Solution Overview
Problem
In semiconductor memory devices, particularly DRAM, ensuring a sufficient area for electrodes has been challenging due to miniaturization, and existing methods struggle to prevent step formation between memory cell and peripheral circuit portions during manufacturing.
Innovation Solution
The solution involves forming a semiconductor memory device with a memory cell portion and a peripheral circuit portion, where capacitors are constructed using a first insulating portion, a lower electrode, a dielectric film, and an upper electrode on the side surfaces of the insulating portion, and a plate electrode, with a method that includes forming openings, depositing conductive materials, and filling insulating materials to create pillar-shaped capacitors in the memory cell portion and cylinder-shaped capacitors in the peripheral circuit portion, ensuring increased contact area and preventing step formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet etching is performed to form openings and expose lower electrode surfaces, then the lower electrode internal surfaces become exposed for capacitor formation, but steps are formed at the boundary between memory cell portion and peripheral circuit portion
Solution Approach 1:
The patent applies different etching conditions to different regions: the memory cell portion uses standard wet etching to expose lower electrode surfaces, while the peripheral circuit portion uses a different etching approach that prevents step formation. This local differentiation allows both requirements to be satisfied simultaneously.
Solution Approach 2:
The etching process is segmented into region-specific operations. The memory cell portion and peripheral circuit portion are processed separately with different etching parameters, allowing the lower electrode surfaces in the memory cell region to be exposed while maintaining planarity in the peripheral circuit region.
2Quantity of substance
If electrode area is increased to ensure sufficient capacity in miniaturized devices, then capacitor capacity increases, but device area consumption increases
Solution Approach 1:
The patent transitions from planar electrode structures to three-dimensional structures with internal surfaces. By forming lower electrodes with exposed internal surfaces in the memory cell portion, the electrode area is increased vertically rather than horizontally, allowing greater capacity without proportionally increasing device footprint.
Solution Approach 2:
The capacitor structure is nested within the three-dimensional lower electrode framework. The dielectric film and upper electrode are formed on the exposed internal surfaces of the lower electrode, creating a nested configuration that maximizes electrode area within the available vertical space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-density capacitor formation, increased electrode areas, and prevents improper formation during subsequent manufacturing steps, such as wet etching, thereby enhancing the stability and miniaturization of the memory device.
Implementation Method 1
depositing a conductive material on an inner wall of each of the first and second openings so as to leave an opening portion unfilled, to form a lower electrode
Implementation Method 2
by performing wet etching, the interlayer insulating film is removed except for the portion of the interlayer insulating film which is located under the mask pattern, to form an opening
Data Source
AI summary
A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined direction, and a transistor electrically connected to the lower electrode. The peripheral circuit portion includes a plate electrode, a cylinder capacitor with an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode which is parallel to the predetermined direction, and a transistor electrically connected to the lower electrode.